公开(公告)号：US20230005872A1

公开(公告)日：2023-01-05

申请号：US17844453

申请日：2022-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongkwan Kim ,  Kunsil Lee

IPC: H01L23/00 ,  H01L23/31 ,  H01L25/18 ,  B32B7/12 ,  C09J7/30

Abstract: A semiconductor package includes: a first substrate; a second substrate including a semiconductor element formed thereon; a film layer between the first substrate and the second substrate; and a molding member surrounding the second substrate, wherein the film layer includes a crystalline spherical silica filler distributed in a matrix.

公开(公告)号：US11935868B2

公开(公告)日：2024-03-19

申请号：US17384046

申请日：2021-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kunsil Lee ,  Dongkwan Kim

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/32 ,  H01L24/73 ,  H01L2224/32145 ,  H01L2224/73204 ,  H01L2225/06513 ,  H01L2225/06517

Abstract: A semiconductor package is disclosed. The semiconductor package includes a base structure, a first semiconductor chip over the base structure, a second semiconductor chip over the first semiconductor chip, an adhesive layer between the first semiconductor chip and the second semiconductor chip, and a molding layer covering the first semiconductor chip, the second semiconductor chip and the adhesive layer, and including an interposition portion interposed between the base structure and the first semiconductor chip.

公开(公告)号：US20230082912A1

公开(公告)日：2023-03-16

申请号：US17724568

申请日：2022-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wongi Chang ,  Dongkwan Kim ,  Jihan Ko ,  Jungseok Ryu ,  Youngmin Lee

IPC: H01L25/065

Abstract: A semiconductor package includes a circuit board including a wiring structure, first and second semiconductor chips disposed on the circuit board and connected to the wiring structure, a dummy chip disposed on the circuit board and positioned between the first and second semiconductor chips, and a molded member disposed on the circuit board and surrounding the first and second semiconductor chips and the dummy chip. The dummy chip may include a rounded edge between an upper surface and a side surface.