公开(公告)号：US20220262699A1

公开(公告)日：2022-08-18

申请号：US17358149

申请日：2021-06-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUNGKYU KIM ,  KYOUNGLIM SUK

IPC: H01L23/367 ,  H01L23/498 ,  H01L23/00 ,  H01L23/31 ,  H01L25/16

Abstract: A semiconductor package includes; a wiring structure including signal wiring and heat transfer wiring, an active chip on the wiring structure, a signal terminal disposed between the wiring structure and the active chip, a first heat transferring terminal disposed between the wiring structure and the active chip and connected to the heat transfer wiring, a passive chip on the wiring structure, a second heat transferring terminal disposed between the wiring structure and the passive chip and connected to the heat transfer wiring, and a heat spreader on the passive chip.

公开(公告)号：US20230207441A1

公开(公告)日：2023-06-29

申请号：US18111100

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGYOUN KIM ,  EUNGKYU KIM ,  GWANGJAE JEON

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L24/16 ,  H01L24/81 ,  H01L24/13 ,  H01L24/17 ,  H01L21/4857 ,  H01L21/481 ,  H01L23/49822 ,  H01L25/18

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a redistribution substrate including dielectric and redistribution patterns, a first substrate pad on the redistribution substrate and penetrating the dielectric pattern to be coupled to the redistribution pattern, a second substrate pad the redistribution substrate and spaced apart from the first substrate pad, a semiconductor chip on the redistribution substrate, a first connection terminal connecting the first substrate pad to one of chip pads of the semiconductor chip, and a second connection terminal connecting the second substrate pad to another one of the chip pads of the semiconductor chip. A top surface of the second substrate pad is located at a higher level than that of a top surface of the first substrate pad. A width of the second substrate pad is less than that of the first substrate pad.

公开(公告)号：US20220084924A1

公开(公告)日：2022-03-17

申请号：US17222912

申请日：2021-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： EUNGKYU KIM ,  JONGYOUN KIM ,  GWANGJAE JEON

IPC: H01L23/498 ,  H01L25/18 ,  H01L21/48

Abstract: A semiconductor package may include a substrate and a semiconductor chip on the substrate. The substrate may include an inner insulating layer, a redistribution layer in the inner insulating layer, an outer insulating layer on the inner insulating layer, a connection pad provided in the outer insulating layer and electrically connected to the redistribution layer, and a ground electrode in the outer insulating layer. A top surface of the connection pad may be exposed by a top surface of the outer insulating layer, and a level of the top surface of the connection pad may be lower than a level of the top surface of the outer insulating layer. A level of a bottom surface of the ground electrode may be higher than a level of a top surface of the redistribution layer, and the outer insulating layer covers a top surface of the ground electrode.

公开(公告)号：US20220059444A1

公开(公告)日：2022-02-24

申请号：US17206291

申请日：2021-03-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGYOUN KIM ,  EUNGKYU KIM ,  GWANGJAE JEON

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a redistribution substrate including dielectric and redistribution patterns, a first substrate pad on the redistribution substrate and penetrating the dielectric pattern to be coupled to the redistribution pattern, a second substrate pad the redistribution substrate and spaced apart from the first substrate pad, a semiconductor chip on the redistribution substrate, a first connection terminal connecting the first substrate pad to one of chip pads of the semiconductor chip, and a second connection terminal connecting the second substrate pad to another one of the chip pads of the semiconductor chip. A top surface of the second substrate pad is located at a higher level than that of a top surface of the first substrate pad. A width of the second substrate pad is less than that of the first substrate pad.