公开(公告)号：US20230005842A1

公开(公告)日：2023-01-05

申请号：US17828799

申请日：2022-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINJUNG KIM ,  DONGKYU KIM ,  JONGYOUN KIM ,  SEOKHYUN LEE ,  JAEGWON JANG

IPC: H01L23/538 ,  H01L25/18

Abstract: A semiconductor package includes a substrate; and a first semiconductor device and a second semiconductor device that are provided on the substrate. The substrate includes a first dielectric layer and a second dielectric layer provided on the first dielectric layer, a plurality of signal lines provided between the first dielectric layer and the second dielectric layer and connecting the first semiconductor device to the second semiconductor device, and a conductive pad and a conductive plate provided on the second dielectric layer. The conductive pad overlaps the first semiconductor device or the second semiconductor device. The conductive plate overlaps the signal lines.

公开(公告)号：US20240371811A1

公开(公告)日：2024-11-07

申请号：US18773989

申请日：2024-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGYOUN KIM

IPC: H01L23/00 ,  H01L23/14 ,  H01L23/498 ,  H01L23/538

Abstract: A semiconductor package includes a redistribution substrate, and a semiconductor chip disposed on a top surface of the redistribution substrate. The redistribution substrate includes under bump patterns laterally spaced apart from each other, a dummy pattern disposed between the under bump patterns, a passivation pattern disposed on a bottom surface of the dummy pattern, an insulating layer covering top surfaces and sidewalls of the under bump patterns and a sidewall and a top surface of the dummy pattern, and a redistribution pattern disposed on one of the under bump patterns and electrically connected to the one under bump pattern. The passivation pattern includes a different material from that of the insulating layer.

公开(公告)号：US20240421061A1

公开(公告)日：2024-12-19

申请号：US18624328

申请日：2024-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JONGYOUN KIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/13 ,  H01L23/14 ,  H01L23/31 ,  H01L25/10

Abstract: A semiconductor package includes a lower redistribution wiring layer having lower redistribution wirings, at least one semiconductor chip disposed on, and electrically connected to, the lower redistribution wiring layer, a sealing member disposed on the lower redistribution wiring layer and having a plurality of through vias that penetrate the sealing member and are electrically connected to the lower redistribution wirings, a dummy substrate layer stacked on the sealing member and the at least one semiconductor chip and having a plurality of through electrodes that penetrate the dummy substrate layer and are electrically connected to the plurality of through vias, and an upper redistribution wiring layer disposed on the dummy substrate layer and having upper redistribution wirings that are electrically connected to the plurality of through electrodes.

公开(公告)号：US20210375810A1

公开(公告)日：2021-12-02

申请号：US17112567

申请日：2020-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGYOUN KIM

IPC: H01L23/00 ,  H01L23/538 ,  H01L23/498 ,  H01L23/14

Abstract: A semiconductor package includes a redistribution substrate, and a semiconductor chip disposed on a top surface of the redistribution substrate. The redistribution substrate includes under bump patterns laterally spaced apart from each other, a dummy pattern disposed between the under bump patterns, a passivation pattern disposed on a bottom surface of the dummy pattern, an insulating layer covering top surfaces and sidewalls of the under bump patterns and a sidewall and a top surface of the dummy pattern, and a redistribution pattern disposed on one of the under bump patterns and electrically connected to the one under bump pattern. The passivation pattern includes a different material from that of the insulating layer.

公开(公告)号：US20230422521A1

公开(公告)日：2023-12-28

申请号：US18165412

申请日：2023-02-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYUNG DON MUN ,  JONGYOUN KIM ,  JAEGWON JANG

IPC: H10B80/00

CPC classification number: H10B80/00

Abstract: A semiconductor package includes a buffer die. One or more first semiconductor dies are stacked on the buffer die such that active surfaces face the buffer die. A second semiconductor die is stacked on the first semiconductor dies. The second semiconductor die includes a first layer and a second layer disposed thereon. The first layer includes a first semiconductor substrate. First memory blocks are disposed on the first semiconductor substrate. A first penetration electrode vertically penetrates the first semiconductor substrate and is connected to the first memory blocks. The second layer includes a second semiconductor substrate and computing blocks disposed on the second semiconductor substrate. The first and second layers have active surfaces in contact with each other. The first memory block aid the computing block have first and second pads, respectively, in contact with each other.

公开(公告)号：US20230207441A1

公开(公告)日：2023-06-29

申请号：US18111100

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGYOUN KIM ,  EUNGKYU KIM ,  GWANGJAE JEON

IPC: H01L23/498 ,  H01L23/00 ,  H01L21/48

CPC classification number: H01L23/49838 ,  H01L24/16 ,  H01L24/81 ,  H01L24/13 ,  H01L24/17 ,  H01L21/4857 ,  H01L21/481 ,  H01L23/49822 ,  H01L25/18

Abstract: Disclosed are semiconductor packages and methods of fabricating the same. The semiconductor package comprises a redistribution substrate including dielectric and redistribution patterns, a first substrate pad on the redistribution substrate and penetrating the dielectric pattern to be coupled to the redistribution pattern, a second substrate pad the redistribution substrate and spaced apart from the first substrate pad, a semiconductor chip on the redistribution substrate, a first connection terminal connecting the first substrate pad to one of chip pads of the semiconductor chip, and a second connection terminal connecting the second substrate pad to another one of the chip pads of the semiconductor chip. A top surface of the second substrate pad is located at a higher level than that of a top surface of the first substrate pad. A width of the second substrate pad is less than that of the first substrate pad.

公开(公告)号：US20230065378A1

公开(公告)日：2023-03-02

申请号：US17680857

申请日：2022-02-25

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINJUNG KIM ,  DONGKYU KIM ,  JONGYOUN KIM ,  SEOKHYUN LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48 ,  H01L23/498

Abstract: A semiconductor package includes a first redistribution substrate, a lower semiconductor chip on the first redistribution substrate and a through via therein, a first lower conductive structure and a second lower conductive structure that are on the first redistribution substrate and are laterally spaced apart from the lower semiconductor chip, an upper semiconductor chip on the lower semiconductor chip and the second lower conductive structure and coupled to the through via and the second lower conductive structure, and an upper conductive structure on the first lower conductive structure. A width of the second lower conductive structure is greater than a width of the through via.

公开(公告)号：US20240222244A1

公开(公告)日：2024-07-04

申请号：US18230416

申请日：2023-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： JONGYOUN KIM

IPC: H01L23/498 ,  H01L23/00 ,  H01L25/10

CPC classification number: H01L23/49822 ,  H01L23/49838 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/73 ,  H01L25/105 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/16238 ,  H01L2224/29011 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/182

Abstract: A semiconductor package includes a first redistribution layer, a first semiconductor chip on the first redistribution layer, a mold layer covering a side surface of the first semiconductor chip and a top surface of the first redistribution layer and having an upper surface coplanar with an upper surface of the first semiconductor chip, a metal layer on the first semiconductor chip and the mold layer to be in contact with upper surfaces of the mold layer and the first semiconductor chip, and a second redistribution layer on the metal layer.

公开(公告)号：US20230101149A1

公开(公告)日：2023-03-30

申请号：US17843967

申请日：2022-06-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： TAEWON YOO ,  JONGYOUN KIM ,  KYOUNG LIM SUK ,  SEOKHYUN LEE ,  HYEONJEONG HWANG

IPC: H01L23/367 ,  H01L25/10 ,  H01L23/31 ,  H01L25/18

Abstract: A semiconductor package is disclosed. The semiconductor package may include a first redistribution substrate including a first insulating layer and a first redistribution pattern, a lower semiconductor chip mounted on the first redistribution substrate, a conductive structure disposed on the first redistribution substrate and horizontally spaced apart from the lower semiconductor chip, a first mold layer interposed between the first redistribution substrate and the second redistribution substrate to cover the lower semiconductor chip and the conductive structure, a second redistribution substrate on the first redistribution substrate, the second redistribution substrate including a second insulating layer and a second redistribution pattern, a first heat-dissipation pattern interposed between the lower semiconductor chip and the second insulating layer, and a heat-dissipation pad on the conductive structure. A top surface of the first heat-dissipation pattern may be located at a level higher than a top surface of the conductive structure.

公开(公告)号：US20220084924A1

公开(公告)日：2022-03-17

申请号：US17222912

申请日：2021-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： EUNGKYU KIM ,  JONGYOUN KIM ,  GWANGJAE JEON

IPC: H01L23/498 ,  H01L25/18 ,  H01L21/48

Abstract: A semiconductor package may include a substrate and a semiconductor chip on the substrate. The substrate may include an inner insulating layer, a redistribution layer in the inner insulating layer, an outer insulating layer on the inner insulating layer, a connection pad provided in the outer insulating layer and electrically connected to the redistribution layer, and a ground electrode in the outer insulating layer. A top surface of the connection pad may be exposed by a top surface of the outer insulating layer, and a level of the top surface of the connection pad may be lower than a level of the top surface of the outer insulating layer. A level of a bottom surface of the ground electrode may be higher than a level of a top surface of the redistribution layer, and the outer insulating layer covers a top surface of the ground electrode.