公开(公告)号：US20240220701A1

公开(公告)日：2024-07-04

申请号：US18533798

申请日：2023-12-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taehyun KIM ,  Hyunjoong KIM ,  Jichull JEONG ,  Euihyun CHEON

IPC: G06F30/392 ,  G06N20/00

CPC classification number: G06F30/392 ,  G06N20/00

Abstract: Disclosed is a method and system for designing a circuit. The method of designing a circuit based on reinforcement learning may include obtaining a state variable of the reinforcement learning, obtaining output data by performing a simulation based on the state variable, calculating a reward variable of the reinforcement learning based on the output data, obtaining an action variable from an agent based on the state variable and the reward variable, training the agent based on the state variable, the reward variable, and the action variable, and updating the state variable based on the action variable, wherein the calculating of the reward variable includes estimating a variation of the circuit based on the state variable, and calculating the reward variable based on the estimated variation.

公开(公告)号：US20240242014A1

公开(公告)日：2024-07-18

申请号：US18537654

申请日：2023-12-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jichull JEONG ,  Hyunjoong KIM ,  Taehyun KIM ,  Euihyun CHEON

IPC: G06F30/392

CPC classification number: G06F30/392

Abstract: Provided is a method of designing an integrated circuit, the method including generating a layout based on data defining a circuit, receiving at least one state variable of reinforcement learning, and updating the layout based on the at least one state variable, wherein the updating of the layout includes modifying the circuit based on the at least one state variable, synchronizing the circuit with the layout, performing a post-layout simulation based on a result of the synchronization, calculating result value of the simulation, and determining whether to modify the at least one state variable through the reinforcement learning according to the result value.

公开(公告)号：US20230221870A1

公开(公告)日：2023-07-13

申请号：US17962872

申请日：2022-10-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euihyun CHEON ,  Sang-Wan NAM

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0679 ,  G06F3/0629

Abstract: Disclosed is a nonvolatile memory device including a memory cell array including memory cells, bit lines and word lines connected with the memory cells, a common source line connected with the memory cells, a control logic circuit including a common source line noise control logic circuit and configured to generate voltages including a first voltage and a second voltage, a voltage selector configured to receive the voltages and configured to select at least one of the voltages, and a common source line driver configured to receive the at least one selected voltage and configured to control a voltage of the common source line, and the common source line noise control logic circuit is configured to control the voltage selector based on program information so as to select the at least one of the voltages.