公开(公告)号：US11277579B2

公开(公告)日：2022-03-15

申请号：US16678384

申请日：2019-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwi Sung Yoo ,  Eun Young Jin

IPC: H01L27/00 ,  H04N5/3745 ,  H04N5/243 ,  H04N5/378

Abstract: An image sensor includes a pixel array configured to generate a plurality of pixel signals, an analog to digital converter circuit coupled to the pixel array and configured to generate respective digital codes responsive to respective ones of the pixel signals, a plurality of memories, respective ones of which are configured to store respective bits of the digital codes, a signal processing circuit coupled to a plurality of memories and configured to generate analog signals responsive to the stored bits, each of the analog signals corresponding to multiple ones of the stored bits, and a comparator circuit configured to compare the analog signals to respective ones of a plurality of reference signals to generate digital signals corresponding to the multiple ones of the stored bits. Related image processing systems and methods are also described.

公开(公告)号：US20200077042A1

公开(公告)日：2020-03-05

申请号：US16678384

申请日：2019-11-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwi Sung Yoo ,  Eun Young Jin

IPC: H04N5/3745 ,  H04N5/378 ,  H04N5/243

Abstract: An image sensor includes a pixel array configured to generate a plurality of pixel signals, an analog to digital converter circuit coupled to the pixel array and configured to generate respective digital codes responsive to respective ones of the pixel signals, a plurality of memories, respective ones of which are configured to store respective bits of the digital codes, a signal processing circuit coupled to a plurality of memories and configured to generate analog signals responsive to the stored bits, each of the analog signals corresponding to multiple ones of the stored bits, and a comparator circuit configured to compare the analog signals to respective ones of a plurality of reference signals to generate digital signals corresponding to the multiple ones of the stored bits. Related image processing systems and methods are also described.

公开(公告)号：US20170148377A1

公开(公告)日：2017-05-25

申请号：US15358906

申请日：2016-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KWI SUNG YOO ,  Dong-Hoon Baek ,  Dong Myung Lee ,  Hyun Wook Lim ,  Eun Young Jin ,  Jae Youl Lee

IPC: G09G3/20

CPC classification number: G09G3/2096 ,  G09G3/2092 ,  G09G2310/0221 ,  G09G2370/08 ,  G09G2370/10

Abstract: A display device includes a data generator configured to generate a clock-embedded data packet, and a controller configured to control operation of the data generator. The data packet comprises a header, a first symbol comprising address information therein, and a second symbol not comprising address information, and the header comprises address information of the first symbol.

公开(公告)号：US10170033B2

公开(公告)日：2019-01-01

申请号：US15358906

申请日：2016-11-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwi Sung Yoo ,  Dong Hoon Baek ,  Dong Myung Lee ,  Hyun Wook Lim ,  Eun Young Jin ,  Jae Youl Lee

IPC: G09G3/20

Abstract: A display device includes a data generator configured to generate a clock-embedded data packet, and a controller configured to control operation of the data generator. The data packet comprises a header, a first symbol comprising address information therein, and a second symbol not comprising address information, and the header comprises address information of the first symbol.

公开(公告)号：US09294703B2

公开(公告)日：2016-03-22

申请号：US14095082

申请日：2013-12-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyo Jin Choo ,  Eun Young Jin

IPC: H04L12/40 ,  H04N5/378 ,  H04N5/374

CPC classification number: H04N5/378 ,  H04N5/3742

Abstract: A data transmission circuit of an image sensor includes first to Kth bus segments, and first to Kth data regeneration circuits respectively connected to the first to Kth bus segments and the first to (K−1)th data regeneration circuits respectively connected to the second to Kth bus segments. Each of the first to Kth data regeneration circuits may be embodied as one of a buffer, a logic gate, and a synchronous circuit operating in response to a clock signal.

Abstract translation: 图像传感器的数据传输电路包括第一至第K总线段，以及分别连接到第一至第K总线段的第一至第K个数据再生电路以及分别连接到第二至第K总线段的第一至第（K-1）个数据再生电路 第七巴士段。 第一至第K数据再生电路中的每一个可以实现为响应于时钟信号而工作的缓冲器，逻辑门和同步电路之一。