公开(公告)号：US20240062806A1

公开(公告)日：2024-02-22

申请号：US18303522

申请日：2023-04-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungki Hong ,  Jinsol Park ,  Jaeseong Lim ,  Minsoo Jang ,  Eunki Hong

IPC: G11C11/4091 ,  G11C11/4096 ,  G11C11/4094

CPC classification number: G11C11/4091 ,  G11C11/4096 ,  G11C11/4094

Abstract: A method of operating a memory device includes precharging a pair of true and complementary bit lines (BL/BLB) to an equivalent voltage concurrently with precharging a pair of true and complementary sense bit lines (SABL/SABLB) to the equivalent voltage, and then transferring charge associated with offset noise from BL to SABLB concurrently with transferring charge associated with the offset noise from BLB to SABL, so that a voltage difference is established between the SABL and SABLB. Next, a logic state of a memory cell connected to BI is read by transferring charge between the memory cell and BL, concurrently with equilibrating voltages on SABL and SABLB. Then, a voltage difference between SABL and SABLB is sensed and amplified in response to activating an amplifier circuit within the sense amplifier.