SEMICONDUCTOR PACKAGE HAVING STIFFENING STRUCTURE

    公开(公告)号:US20210151388A1

    公开(公告)日:2021-05-20

    申请号:US16848106

    申请日:2020-04-14

    摘要: A semiconductor package having a stiffening structure is disclosed. The semiconductor package includes a substrate, an interposer on the substrate, and a first logic chip, a second logic chip, memory stacks and stiffening chips, all of which are on the interposer. The first logic chip and the second logic chip are adjacent to each other. Each memory stack is adjacent to a corresponding one of the first logic chip and the second logic chip. Each memory stack includes a plurality of stacked memory chips. Each stiffening chip is disposed between corresponding ones of the memory stacks, to be aligned and overlap with a boundary area between the first logic chip and the second logic chip.

    SEMICONDUCTOR PACKAGE HAVING STIFFENER STRUCTURE

    公开(公告)号:US20220399287A1

    公开(公告)日:2022-12-15

    申请号:US17576113

    申请日:2022-01-14

    发明人: Eunkyoung CHOI

    摘要: A semiconductor package including a package base substrate, an interposer on the package base substrate, a plurality of semiconductor chips on the interposer, and a stiffener structure including a stiffener frame and a stiffener extension portion, the stiffener frame being on the package base substrate and apart from the interposer, the stiffener extension portion extending from the stiffener frame, spaced apart from the plurality of semiconductor chips, and extending onto the interposer to have a portion on the interposer, and the stiffener frame being an integral structure with the extension portion, may be provided.

    SEMICONDUCTOR PACKAGE HAVING STIFFENING STRUCTURE

    公开(公告)号:US20220223543A1

    公开(公告)日:2022-07-14

    申请号:US17705770

    申请日:2022-03-28

    摘要: A semiconductor package having a stiffening structure is disclosed. The semiconductor package includes a substrate, an interposer on the substrate, and a first logic chip, a second logic chip, memory stacks and stiffening chips, all of which are on the interposer. The first logic chip and the second logic chip are adjacent to each other. Each memory stack is adjacent to a corresponding one of the first logic chip and the second logic chip. Each memory stack includes a plurality of stacked memory chips. Each stiffening chip is disposed between corresponding ones of the memory stacks, to be aligned and overlap with a boundary area between the first logic chip and the second logic chip.