公开(公告)号：US20210151388A1

公开(公告)日：2021-05-20

申请号：US16848106

申请日：2020-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunkyoung CHOI ,  Suchang LEE ,  Yunseok CHOI

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H01L23/16 ,  H01L23/498

Abstract: A semiconductor package having a stiffening structure is disclosed. The semiconductor package includes a substrate, an interposer on the substrate, and a first logic chip, a second logic chip, memory stacks and stiffening chips, all of which are on the interposer. The first logic chip and the second logic chip are adjacent to each other. Each memory stack is adjacent to a corresponding one of the first logic chip and the second logic chip. Each memory stack includes a plurality of stacked memory chips. Each stiffening chip is disposed between corresponding ones of the memory stacks, to be aligned and overlap with a boundary area between the first logic chip and the second logic chip.

公开(公告)号：US20210305117A1

公开(公告)日：2021-09-30

申请号：US17060805

申请日：2020-10-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Suchang LEE ,  Dongok KWAK

IPC: H01L23/36 ,  H01L23/538

Abstract: A semiconductor package includes a substrate including an upper surface and a side surface, an adhesive layer disposed on an edge of the upper surface of the substrate, and a stiffener including a horizontal portion disposed on the adhesive layer and extending in an horizontal direction to an outside of the substrate in a plan view and a vertical portion connected to the horizontal portion and extending vertically downwards from the horizontal portion. The vertical portion is spaced apart from the side surface of the substrate with a vertical gap extending in a vertical direction therebetween, and the outer width of the stiffener is 40 mm or more.

公开(公告)号：US20220223543A1

公开(公告)日：2022-07-14

申请号：US17705770

申请日：2022-03-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunkyoung CHOI ,  Suchang LEE ,  Yunseok CHOI

IPC: H01L23/00 ,  H01L23/16 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package having a stiffening structure is disclosed. The semiconductor package includes a substrate, an interposer on the substrate, and a first logic chip, a second logic chip, memory stacks and stiffening chips, all of which are on the interposer. The first logic chip and the second logic chip are adjacent to each other. Each memory stack is adjacent to a corresponding one of the first logic chip and the second logic chip. Each memory stack includes a plurality of stacked memory chips. Each stiffening chip is disposed between corresponding ones of the memory stacks, to be aligned and overlap with a boundary area between the first logic chip and the second logic chip.