公开(公告)号：US20220085025A1

公开(公告)日：2022-03-17

申请号：US17225601

申请日：2021-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunseok LIM ,  Minhyuk CHO ,  Kyung-Eun BYUN ,  Hyeonjin SHIN ,  Kaoru YAMAMOTO ,  Jungsoo YOON ,  Soyoung LEE ,  Geuno JEONG

IPC: H01L27/108

Abstract: A wiring structure includes a first conductive pattern including doped polysilicon on a substrate, an ohmic contact pattern including a metal silicide on the first conductive pattern, an oxidation prevention pattern including a metal silicon nitride on the ohmic contact pattern, a diffusion barrier including graphene on the oxidation prevention pattern, and a second conductive pattern including a metal on the diffusion barrier.

公开(公告)号：US20230102650A1

公开(公告)日：2023-03-30

申请号：US17954960

申请日：2022-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Geuno JEONG ,  Janghee LEE ,  Sungjoo AN ,  Seran OH

IPC: H01L21/02 ,  H01L21/687 ,  C23C16/458 ,  C23C16/02 ,  C23C16/455 ,  C23C16/46 ,  C23C16/26

Abstract: A substrate processing apparatus includes: configured to support a plurality of substrates; a chamber sidewall surrounding at least a side surface of the substrate support; and an upper plate including a plurality of plate portions on the substrate support and spaced apart from the substrate support. The plurality of plate portions and the substrate support collectively at least partially define a plurality of process regions between the plurality of plate portions and the substrate support and a separation between at least two process regions of the plurality of process regions. The plurality of process regions include a pretreatment process region between the pretreatment process plate portion and the substrate support and having a first height, and a deposition process region between the deposition process plate portion and the substrate support and having a second height, greater than the first height.