公开(公告)号：US20240038903A1

公开(公告)日：2024-02-01

申请号：US18483058

申请日：2023-10-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Hyeonjin SHIN ,  Minseok YOO ,  Minhyun LEE

IPC: H01L29/786 ,  H01L29/41 ,  H01L29/417 ,  H01L29/24 ,  H01L29/66 ,  H01L29/45 ,  H01L29/06 ,  H01L21/02 ,  H01L21/8234 ,  H01L29/16

CPC classification number: H01L29/78696 ,  H01L29/413 ,  H01L29/41733 ,  H01L29/24 ,  H01L29/66969 ,  H01L29/45 ,  H01L29/0665 ,  H01L21/02417 ,  H01L21/02568 ,  H01L21/823412 ,  H01L29/1606

Abstract: Provided are two-dimensional material (2D)-based wiring conductive layer contact structures, electronic devices including the same, and methods of manufacturing the electronic devices. A 2D material-based field effect transistor includes a substrate; first to third 2D material layers on the substrate; an insulating layer on the first 2D material layer; a source electrode on the second 2D material layer; a drain electrode on the third 2D material layer; and a gate electrode on the insulating layer. The first 2D material layer is configured to exhibit semiconductor characteristics, and the second and third 2D material layers are metallic 2D material layers. The first 2D material layer may include a first channel layer of a 2D material and a second channel layer of a 2D material. The first 2D material layer may partially overlap the second and third 2D material layers.

公开(公告)号：US20230395665A1

公开(公告)日：2023-12-07

申请号：US18052017

申请日：2022-11-02

Applicant: Samsung Electronics Co., Ltd. ,  THE UNIVERSITY OF CHICAGO ,  Center for Technology Licensing at Cornell University

Inventor： Minhyun LEE ,  Jiwoong PARK ,  Saien XIE ,  Jinseong HEO ,  Hyeonjin SHIN

IPC: H01L29/15 ,  H01L29/10

CPC classification number: H01L29/158 ,  H01L29/1054

Abstract: Provided are a superlattice structure including a two-dimensional material and a device including the superlattice structure. The superlattice structure may include at least two different two-dimensional (2D) materials bonded to each other in a lateral direction, and an interfacial region of the at least two 2D materials may be strained. The superlattice structure may have a bandgap adjusted by the interfacial region that is strained. The at least two 2D materials may include first and second 2D materials. The first 2D material may have a first bandgap in an intrinsic state thereof. The second 2D material may have a second bandgap in an intrinsic state thereof. An interfacial region of the first and second 2D materials and an adjacent region may have a third bandgap between the first bandgap and the second bandgap.

公开(公告)号：US20230041352A1

公开(公告)日：2023-02-09

申请号：US17565807

申请日：2021-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Seunggeol NAM ,  Kyung-Eun BYUN ,  Hyeonjin SHIN

IPC: H01L23/528 ,  H01L23/532

Abstract: Provided are an interconnect structure and an electronic device including the interconnect structure. The interconnect structure may include a dielectric layer including a trench; a conductive line in the trench; and a first cap layer on an upper surface of the conductive line. The first cap layer may include a graphene-metal composite including graphene and a metal mixed with each other.

公开(公告)号：US20230017244A1

公开(公告)日：2023-01-19

申请号：US17552756

申请日：2021-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keunwook SHIN ,  Hyeonjin SHIN ,  Alum JUNG ,  Changseok LEE

IPC: H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  C01B32/186 ,  C23C16/26 ,  C23C16/505 ,  C23C16/511 ,  C23C16/02

Abstract: A method of forming nanocrystalline graphene according to an embodiment may include: arranging a substrate having a pattern in a reaction chamber; injecting a reaction gas into the reaction chamber, where the reaction gas includes a carbon source gas, an inert gas, and a hydrogen gas that are mixed; generating a plasma of the reaction gas in the reaction chamber; and directly growing the nanocrystalline graphene on a surface of the pattern using the plasma of the reaction gas at a process temperature. The pattern may include a first material and the substrate may include a second material different from the first material.

公开(公告)号：US20220333010A1

公开(公告)日：2022-10-20

申请号：US17720518

申请日：2022-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangwon KIM ,  Xinliang FENG ,  Fupeng WU ,  Junzhi LIU ,  Klaus MUELLEN ,  Wenhui NIU ,  Hyeonjin SHIN

IPC: C09K11/65 ,  C01B32/182

Abstract: Provided are soluble graphene quantum dots and light-emitting devices including the same. The soluble graphene quantum dot has an anthracenyl N-alkyl maleimide functional group at an edge thereof, thereby exhibiting improved solubility and/or improved emission characteristics.

公开(公告)号：US20220328671A1

公开(公告)日：2022-10-13

申请号：US17539768

申请日：2021-12-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhyun KIM ,  Hyeonjin SHIN ,  Minhyun LEE ,  Taejin CHOI ,  Sangwon KIM ,  Bongseob YANG ,  Eunkyu LEE

IPC: H01L29/76 ,  H01L27/092 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L29/16 ,  H01L29/20 ,  H01L29/24

Abstract: A field effect transistor structure is disclosed. The field effect transistor structure includes: a fin-shaped channel protruding from a substrate and extending in one direction; a source electrode on one side of the fin-shaped channel; a drain electrode separated from the source electrode with the fin-shaped channel therebetween; a gate insulating film surrounding side and upper surfaces of the fin-shaped channel; a gate electrode on the gate insulating film; and a two-dimensional semiconductor material layer between the gate insulating film and the gate electrode.

公开(公告)号：US20220262903A1

公开(公告)日：2022-08-18

申请号：US17735475

申请日：2022-05-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minhyun LEE ,  Haeryong KIM ,  Hyeonjin SHIN ,  Seunggeol NAM ,  Seongjun PARK

IPC: H01L29/08 ,  H01L21/285 ,  H01L29/45 ,  H01L29/417 ,  H01L29/04 ,  H01L29/06 ,  H01L29/267 ,  H01L29/78

Abstract: A semiconductor device includes a semiconductor layer, a metal layer electrically contacting the semiconductor layer, and a two-dimensional material layer between the semiconductor layer and the metal layer and having a two-dimensional crystal structure.

公开(公告)号：US20220085025A1

公开(公告)日：2022-03-17

申请号：US17225601

申请日：2021-04-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunseok LIM ,  Minhyuk CHO ,  Kyung-Eun BYUN ,  Hyeonjin SHIN ,  Kaoru YAMAMOTO ,  Jungsoo YOON ,  Soyoung LEE ,  Geuno JEONG

IPC: H01L27/108

Abstract: A wiring structure includes a first conductive pattern including doped polysilicon on a substrate, an ohmic contact pattern including a metal silicide on the first conductive pattern, an oxidation prevention pattern including a metal silicon nitride on the ohmic contact pattern, a diffusion barrier including graphene on the oxidation prevention pattern, and a second conductive pattern including a metal on the diffusion barrier.

公开(公告)号：US20220077321A1

公开(公告)日：2022-03-10

申请号：US17370480

申请日：2021-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Minsu SEOL ,  Minhyun LEE ,  Junyoung KWON ,  Hyeonjin SHIN ,  Minseok YOO

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/16 ,  H01L29/24 ,  H01L29/423 ,  H01L29/76 ,  H01L21/02 ,  H01L29/66

Abstract: Disclosed are a field effect transistor and a method of manufacturing the same. The field effect transistor includes a source electrode on a substrate, a drain electrode separated from the source electrode, and channels connected between the source electrode and the drain electrode, gate insulating layers, and a gate electrode. The channels may have a hollow closed cross-sectional structure when viewed in a first cross-section formed by a plane across the source electrode and the drain electrode in a direction perpendicular to the substrate. The gate insulating layers may be in the channels. The gate electrode may be insulated from the source electrode and the drain electrode by the gate insulating layers.

公开(公告)号：US20220068633A1

公开(公告)日：2022-03-03

申请号：US17382793

申请日：2021-07-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeonjin SHIN ,  Keunwook SHIN

IPC: H01L21/027 ,  H01L21/768

Abstract: Provided are a method of forming a carbon layer and a method of forming an interconnect structure. The method of forming a carbon layer includes providing a substrate including first and second material layers, forming a surface treatment layer on at least one of the first and second material layers, and selectively forming a carbon layer on one of the first material layer and the second material layer. The carbon layer has an sp2 bonding structure.