公开(公告)号：US12119048B2

公开(公告)日：2024-10-15

申请号：US17964092

申请日：2022-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghan Kim ,  Gunhee Cho

IPC: G11C11/408 ,  G11C11/4093 ,  G11C11/4076 ,  G11C11/4096

CPC classification number: G11C11/4093 ,  G11C11/4082 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096

Abstract: A semiconductor memory device includes a data input/output (I/O) buffer, a data first-in/first-out (FIFO) circuit, an address comparing circuit. The data I/O buffer provides a memory cell array with write data. The data FIFO circuit includes plurality of data FIFO buffers which store read data that is read from the memory cell array in each of a plurality of read operations. The data FIFO circuit outputs data stored in one of the plurality of data FIFO buffers based on a plurality of sub matching signals. The address comparing circuit sequentially stores previous addresses accompanied by first commands designating the plurality of read operations and generates the plurality of sub matching signals based on a comparison of the previous addresses and a present address accompanied by a second command designating a present read operation.

公开(公告)号：US20250014634A1

公开(公告)日：2025-01-09

申请号：US18887410

申请日：2024-09-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghan Kim ,  Gunhee Cho

IPC: G11C11/4093 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4096

Abstract: A semiconductor memory device includes a data input/output (I/O) buffer, a data first-in/first-out (FIFO) circuit, an address comparing circuit. The data I/O buffer provides a memory cell array with write data. The data FIFO circuit includes plurality of data FIFO buffers which store read data that is read from the memory cell array in each of a plurality of read operations. The data FIFO circuit outputs data stored in one of the plurality of data FIFO buffers based on a plurality of sub matching signals. The address comparing circuit sequentially stores previous addresses accompanied by first commands designating the plurality of read operations and generates the plurality of sub matching signals based on a comparison of the previous addresses and a present address accompanied by a second command designating a present read operation.

公开(公告)号：US20230335181A1

公开(公告)日：2023-10-19

申请号：US17964092

申请日：2022-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seunghan Kim ,  Gunhee Cho

IPC: G11C11/4093 ,  G11C11/408

CPC classification number: G11C11/4093 ,  G11C11/4082

Abstract: A semiconductor memory device includes a data input/output (I/O) buffer, a data first-in/first-out (FIFO) circuit, an address comparing circuit. The data I/O buffer provides a memory cell array with write data. The data FIFO circuit includes plurality of data FIFO buffers which store read data that is read from the memory cell array in each of a plurality of read operations. The data FIFO circuit outputs data stored in one of the plurality of data FIFO buffers based on a plurality of sub matching signals. The address comparing circuit sequentially stores previous addresses accompanied by first commands designating the plurality of read operations and generates the plurality of sub matching signals based on a comparison of the previous addresses and a present address accompanied by a second command designating a present read operation.