公开(公告)号：US20230127606A1

公开(公告)日：2023-04-27

申请号：US17837163

申请日：2022-06-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyeongmin NAM ,  Chanha Kim ,  Seungryong Jang

IPC: G06F12/02 ,  G06F12/109 ,  G06F12/123

Abstract: A storage device including: a memory device including memory blocks having different bit densities; and a controller, the controller including: a memory to store a logical address list including a number of recently received logical addresses and a hotness table including a hotness of each of the logical addresses in the list; and a processor to receive a write command, a latest logical address and data, to update a hotness of the latest logical address in the hotness table, to insert the latest logical address into the logical address list, and to control the memory device to program the data into one of the memory blocks depending on whether the hotness of the latest logical address exceeds a threshold value, the hotness of the latest logical address being updated based on how long ago a logical address the same as the latest logical address was received.

公开(公告)号：US20230126807A1

公开(公告)日：2023-04-27

申请号：US17853227

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanha KIM ,  Gyeongmin NAM ,  Seungryong JANG

IPC: G06F12/14 ,  G06F12/0882 ,  G06F12/123

Abstract: A storage device includes a memory device including a first memory region having a lowest bit density, a second memory region having a medium bit density, and a third memory region having a highest bit density, and a controller configured to control the memory device. The controller is configured to determine data from a host as being any one of hot data, warm data and cold data, is configured to store the hot data in the first memory region, is configured to store the warm data in the second memory region, is configured to store the cold data in the third memory region, is configured to select a source block of first memory blocks included in the first memory region, is configured to select destination blocks in each of the second and third memory regions, and is configured to migrate each piece of unit data stored in the source block to one of the destination blocks according to a degree of hotness of each piece of the unit data.

公开(公告)号：US20230130233A1

公开(公告)日：2023-04-27

申请号：US17853195

申请日：2022-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeongmin NAM ,  Chanha KIM ,  Seungryong JANG

IPC: G06F12/02 ,  G06F12/06 ,  G06F12/121

Abstract: A method of operating a storage device, including a first memory region having a lowest bit density, a second memory region having a medium bit density, and a third memory region having a highest bit density, includes determining a hotness of a logical address received with a write command and data to be written, from a host, based on the determined hotness being greater than a first hotness threshold, determining whether a wear level of the first memory region is greater than a wear threshold, and increasing the first hotness threshold and storing the data in the second memory region based on the wear level of the first memory region being greater than a threshold.

公开(公告)号：US20230127449A1

公开(公告)日：2023-04-27

申请号：US17741755

申请日：2022-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chanha KIM ,  Gyeongmin NAM ,  Seungryong JANG

IPC: G06F3/06 ,  G06F12/02

Abstract: A controller includes a central processing unit (CPU) configured to insert a latest received logical address, received together with a write command and data from a host, into a logical address list; a hotness determining circuit configured to assign a maximum weight to the latest received logical address, decrease weights of received logical addresses included in the logical address list by a decay factor, and sum weights of the received logical addresses having values, equal to a value of the latest received logical address, to determine hotness of the latest received logical address; and a parameter adjustment circuit decreasing a magnitude of the decay factor based on the repeatability index of the received logical addresses included in the logical address list, wherein the CPU is configured to control the memory device to store the data in one of the memory regions based on the hotness.