公开(公告)号：US20220083260A1

公开(公告)日：2022-03-17

申请号：US17245325

申请日：2021-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haesuk LEE ,  Reum OH ,  Youngcheon KWON ,  Beomyong KIL ,  Jemin RYU ,  Jihyun CHOI

IPC: G06F3/06

Abstract: A semiconductor memory device includes an interface semiconductor die, at least one memory semiconductor die, and through-silicon vias connecting the interface semiconductor die and the memory semiconductor die. The interface semiconductor die includes command pins to receive command signals transferred from a memory controller and an interface command decoder to decode the command signals. The memory semiconductor die includes a memory integrated circuit configured to store data and a memory command decoder to decode the command signals transferred from the interface semiconductor die. The interface semiconductor die does not include a clock enable pin to receive a clock enable signal from the memory controller. The interface and memory command decoders generate interface and memory clock enable signals to control clock supply with respect to the interface and memory semiconductor dies based on a power mode command transferred through the plurality of command pins from the memory controller.

公开(公告)号：US20190303042A1

公开(公告)日：2019-10-03

申请号：US16197877

申请日：2018-11-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： So-young KIM ,  Reum OH ,  Haesuk LEE

IPC: G06F3/06 ,  H01L25/18 ,  G11C11/4093 ,  G11C11/4076 ,  H01L23/48 ,  G11C11/408 ,  H01L25/065

Abstract: A memory die of a memory device includes a first first-in first-out (FIFO) circuit that samples data output from a memory cell array and outputs the data to a buffer die through a first through silicon via, based on a control signal transmitted from the buffer die. A buffer die of the memory device includes a second FIFO circuit that samples the data output from the first FIFO unit based on the control signal transmitted from the memory die through a second through silicon via, a calibration circuit that generates a delay code, based on a latency of a path from the buffer die to the first FIFO circuit and from the first FIFO circuit to the second FIFO circuit, and a delay control circuit that generates the control signal transmitted to the memory die through a third through silicon via, based on the read command and the delay code.

公开(公告)号：US20210225418A1

公开(公告)日：2021-07-22

申请号：US17145941

申请日：2021-01-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Youngcheon KWON ,  Jemin RYU ,  Jaeyoun YOUN ,  Haesuk LEE ,  Jihyun CHOI

IPC: G11C7/22 ,  G11C7/10

Abstract: A method of operating a memory device including row pins and column pins includes receiving a first active command through the row pins during 1.5 cycles of a clock signal, receiving a first read command or a first write command through the column pins during 1 cycle of the clock signal, receiving a first precharge command through the row pins during a 0.5 cycle of the clock signal corresponding to a rising edge of the clock signal, receiving a second active command through the row pins during the 1.5 cycles of the clock signal, receiving a second read command or a second write command through the column pins during the 1 cycle of the clock signal, and receiving a second precharge command through the row pins during the 0.5 cycle of the clock signal corresponding to a falling edge of the clock signal.

公开(公告)号：US20210216243A1

公开(公告)日：2021-07-15

申请号：US17014667

申请日：2020-09-08

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunsung SHIN ,  Sanghyuk KWON ,  Youngcheon KWON ,  Sukhan LEE ,  Haesuk LEE

IPC: G06F3/06 ,  G06N3/02

Abstract: A memory device includes a memory bank including a plurality of banks, each including a memory cell array; a calculation logic including a plurality of processor-in-memory (PIM) circuits arranged in correspondence to the banks, each of the plurality of PIM circuits performing calculation processing using at least one selected from data provided from a host and information read from a corresponding bank among the banks; and a control logic configured to control a memory operation on the memory bank in response to a command and/or an address, each received from the host, or to control the calculation logic to perform the calculation processing, wherein reading operations are respectively performed in parallel on the banks for the calculation processing, offsets having different values are respectively configured for the banks, and information is read from different positions in respective memory cell arrays of the banks and provided to the PIM circuits.

公开(公告)号：US20190096853A1

公开(公告)日：2019-03-28

申请号：US16044886

申请日：2018-07-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haesuk LEE ,  So-Young KIM ,  Seung-Han WOO

IPC: H01L25/065 ,  G11C5/02 ,  H01L23/538

Abstract: A stacked semiconductor device includes a plurality of semiconductor dies stacked in a first direction, M data paths electrically connecting the plurality of semiconductor dies, one data path including one or more through-silicon vias, where M is a positive integer, a transmission circuit including M serialization units configured to serialize P transmission signals to M serial signals and output the M serial signals to the M data paths, respectively, where P is a positive integer greater than M and a reception circuit including M parallelization units configured to receive the M serial signals from the M data paths and parallelize the M serial signals to P reception signals corresponding to the P transmission signals. The number of the through-silicon vias is reduced by serializing the transmission signals, transferring the serialized signals through the smaller number of data paths between the stacked semiconductor dies and then parallelizing the transferred signals.