公开(公告)号：US20250159861A1

公开(公告)日：2025-05-15

申请号：US18825173

申请日：2024-09-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Keonhee Park ,  Haewook Jeong

IPC: H10B12/00

Abstract: A semiconductor device includes first and second bit lines, a word line, first and second channels and a capacitor. The first and second bit lines extend primarily in a first direction and are spaced apart from each other in a second direction on a substrate. The word line includes first extension portions extending primarily in a third direction, between the first and second bit lines, and a second extension portion extending primarily in the second direction at the same level as the first extension portions and is connected thereto. Each of the first and second channels extends through the first extension portions. The capacitor includes a first capacitor electrode electrically connected to the first channel, a dielectric pattern disposed on a surface of the first capacitor electrode, and a second capacitor electrode disposed on a surface of the dielectric pattern and electrically connected to the second channel.

公开(公告)号：US20250118342A1

公开(公告)日：2025-04-10

申请号：US18633650

申请日：2024-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haewook Jeong ,  Changyoung Lee

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/12

Abstract: A sense amplifier connected to a bit line and a complementary bit line, the sense amplifier including a first transistor connected between the bit line and a first node and including a first gate terminal connected to a third node, a second transistor connected between the first node and the complementary bit line and including a second gate terminal connected to a fourth node, third transistor connected between the bit line and a second node and including a third gate terminal connected to the third node, and a fourth transistor connected between the complementary bit line and the second node and including a fourth gate terminal connected to the fourth node, wherein first and second RC values viewed from the sense amplifier toward the bit line and the complementary bit line differ, and wherein the second transistor is configured to receive a program voltage during a first time period.