公开(公告)号：US20250140332A1

公开(公告)日：2025-05-01

申请号：US18799907

申请日：2024-08-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changyoung Lee ,  Sanghoon Jung ,  Changsik Yoo

IPC: G11C29/12 ,  H01L21/66 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18 ,  H10B80/00

Abstract: An example memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a memory cell array, a first bonding pad, and a first test pad. The second semiconductor layer is disposed with respect to the first semiconductor layer in a vertical direction, and includes a peripheral circuit, a second bonding pad connected to the first bonding pad, a second test pad connected to the first test pad, and a test circuit. The test circuit checks a connection state of the first and second bonding pads. The test circuit receives a first test signal through the first and second test pads, generates a first test result signal representing a first misalignment between the first and second bonding pads based on the first test signal, and compensates an operation of the peripheral circuit based on the first test result signal.

公开(公告)号：US20250124969A1

公开(公告)日：2025-04-17

申请号：US18669633

申请日：2024-05-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changyoung Lee ,  Yeongwoo Kang ,  Yongjun Kim

IPC: G11C11/4091 ,  G11C11/408

Abstract: Memory devices and methods of operating thereof. A memory device may include a plurality of memory cells each including a cell transistor having a back gate that is shared with a cell transistor of an adjacent memory cell through a back gate line, a forward gate that is connected to a corresponding word line, and a cell capacitor that is connected to a first electrode of the cell transistor; a sub-word line driver configured to apply a word line driving voltage to a selected word line; a back gate driver configured to change a back gate voltage applied to the back gate line from a first voltage level to a second voltage level during an active period in which the selected word line is enabled; and a sense amplifier configured to sense data through bit lines connected to second electrodes of the cell transistors of the plurality of memory cells.

公开(公告)号：US20250056795A1

公开(公告)日：2025-02-13

申请号：US18441968

申请日：2024-02-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changyoung Lee ,  Hyun-Chul Yoon ,  Yeongwoo Kang

IPC: H10B20/00 ,  G11C29/04 ,  H10B12/00 ,  H10B20/25

Abstract: The present disclosure relates to memory devices. An example memory device includes a memory cell region including a memory cell array is configured to store data, and an antifuse cell array including a plurality of antifuse bit lines, a plurality of antifuse word lines, and a plurality of program transistors that is electrically coupled to a first antifuse bit line among the plurality of antifuse bit lines and that are coupled in parallel with one another. The memory device includes a peripheral circuit region including an antifuse sense amplifier is configured to output one-time programmable (OTP) data stored in the plurality of program transistors.

公开(公告)号：US20230420034A1

公开(公告)日：2023-12-28

申请号：US18045846

申请日：2022-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changyoung Lee ,  Kyu-Chang Kang ,  Donghak Shin ,  Hyun-Chul Yoon

IPC: G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

CPC classification number: G11C11/4091 ,  G11C11/4094 ,  G11C11/4097

Abstract: In a sense amplifier circuit, a first transistor is electrically connected between a first bitline and a first node, a first inverter includes a first input terminal and a first output terminal connected to the first node, and a second inverter includes a second input terminal connected to a second node and a second output terminal. A second transistor is electrically connected between the first output terminal and the second node, and a third transistor is electrically connected between the second output terminal and the first node. A precharge circuit transfers a first voltage to the first and second nodes during a first period, and transfers a second voltage higher than the first voltage to the first and second nodes during a second period.

公开(公告)号：US20250151292A1

公开(公告)日：2025-05-08

申请号：US18732795

申请日：2024-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changyoung Lee ,  Keonwoo Park ,  Hyunchul Yoon

IPC: H10B80/00 ,  G06F11/10 ,  G11C11/408 ,  G11C11/4091 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A memory device includes a first semiconductor layer and a second semiconductor layer. The first semiconductor layer includes a memory cell array. The memory cell array is connected to a plurality of wordlines and a plurality of bitlines, and includes a plurality of normal memory cells storing normal data and a plurality of error correction code (ECC) memory cells storing ECC data. The second semiconductor layer is disposed with respect to the first semiconductor layer in a vertical direction, and includes a peripheral circuit. The peripheral circuit controls the memory cell array, and includes a row decoder. At least a portion of a region in which the plurality of ECC memory cells are disposed in the first semiconductor layer and at least a portion of a region in which the row decoder is disposed in the second semiconductor layer overlap in a plan view.

公开(公告)号：US12237000B2

公开(公告)日：2025-02-25

申请号：US18045846

申请日：2022-10-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changyoung Lee ,  Kyu-Chang Kang ,  Donghak Shin ,  Hyun-Chul Yoon

IPC: G11C7/06 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4097 ,  G11C7/10

Abstract: In a sense amplifier circuit, a first transistor is electrically connected between a first bitline and a first node, a first inverter includes a first input terminal and a first output terminal connected to the first node, and a second inverter includes a second input terminal connected to a second node and a second output terminal. A second transistor is electrically connected between the first output terminal and the second node, and a third transistor is electrically connected between the second output terminal and the first node. A precharge circuit transfers a first voltage to the first and second nodes during a first period, and transfers a second voltage higher than the first voltage to the first and second nodes during a second period.

公开(公告)号：US20240096402A1

公开(公告)日：2024-03-21

申请号：US18240045

申请日：2023-08-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Changyoung Lee ,  Kyuchang Kang

IPC: G11C11/4091 ,  G11C11/4094

CPC classification number: G11C11/4091 ,  G11C11/4094

Abstract: A sense amplifier includes a first isolation transistor connected to a first memory cell through a first bit line, a second isolation transistor connected to a second memory cell through a second bit line, and sense amplifying circuitry connected to the first memory cell through the first isolation transistor, connected to the second memory cell through the second isolation transistor, and latch, to a pair of sense bit lines, data corresponding to a cell voltage stored in the first memory cell or the second memory cell, wherein the sense amplifying circuitry is configured to perform an offset cancellation operation while a charge sharing operation is performed between the first memory cell and the first bit line or between the second memory cell and the second bit line.

公开(公告)号：US20250166693A1

公开(公告)日：2025-05-22

申请号：US18781150

申请日：2024-07-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sanghoon Jung ,  Changyoung Lee ,  Jeongdon Ihm

IPC: G11C11/408 ,  H01L23/00 ,  H03K19/20

Abstract: A memory device includes a row decoder connected to a plurality of word lines of each of a plurality of memory blocks. The row decoder includes a main word line driver circuit commonly connected to the plurality of memory blocks and configured to generate first main word line driving signals, second main word line driving signals, and sub-word line driving signals based on row address signals, and a sub-word line driving signal connected to each of the plurality of memory blocks and configured to activate one word line from among the plurality of word lines using a NOR logic circuit to which the first main word line driving signals, the second main word line driving signals, and the sub-word line driving signals are connected.

公开(公告)号：US20250118342A1

公开(公告)日：2025-04-10

申请号：US18633650

申请日：2024-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Haewook Jeong ,  Changyoung Lee

IPC: G11C7/06 ,  G11C7/08 ,  G11C7/12

Abstract: A sense amplifier connected to a bit line and a complementary bit line, the sense amplifier including a first transistor connected between the bit line and a first node and including a first gate terminal connected to a third node, a second transistor connected between the first node and the complementary bit line and including a second gate terminal connected to a fourth node, third transistor connected between the bit line and a second node and including a third gate terminal connected to the third node, and a fourth transistor connected between the complementary bit line and the second node and including a fourth gate terminal connected to the fourth node, wherein first and second RC values viewed from the sense amplifier toward the bit line and the complementary bit line differ, and wherein the second transistor is configured to receive a program voltage during a first time period.