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    COMPILATION METHOD AND APPARATUS WITH NEURAL NETWORK
    1.
    发明公开
    COMPILATION METHOD AND APPARATUS WITH NEURAL NETWORK 审中-公开

    公开(公告)号：US20230418579A1

    公开(公告)日：2023-12-28

    申请号：US18464044

    申请日：2023-09-08

    申请人： SAMSUNG ELECTRONICS CO., LTD.

    发明人： Hanwoong JUNG

    IPC分类号： G06F8/41 ,  G06N3/10

    CPC分类号： G06F8/443 ,  G06N3/10 ,  G06F8/451

    摘要： A compile method for a neural network, the compile method includes receiving data related to the neural network, generating a grouped layer by grouping layers comprised in the neural network based on the data, generating a set of passes executable in parallel based on a dependency between a plurality of passes to process the neural network, generating a set of threads performing a plurality of optimization functions based on whether optimization operations performed by the optimization functions is performed independently for the layers, respectively, or sequentially based on a dependency between the layers, and performing compilation in parallel based on the grouped layer, the set of passes, and the set of threads.

    METHOD FOR REALIZING NGRAPH FRAMEWORK SUPPORTING FPGA REAR-END DEVICE
    5.
    发明公开
    METHOD FOR REALIZING NGRAPH FRAMEWORK SUPPORTING FPGA REAR-END DEVICE 审中-公开

    公开(公告)号：US20230267024A1

    公开(公告)日：2023-08-24

    申请号：US18012924

    申请日：2020-10-27

    申请人： INSPUR ELECTRONIC INFORMATION INDUSTRY CO., LTD.

    发明人： Fang CAO ,  Zhenhua GUO ,  Li WANG ,  Kai GAO

    IPC分类号： G06F9/54 ,  G06F8/41

    CPC分类号： G06F9/547 ,  G06F8/451

    摘要： Disclosed are a method for realizing an nGraph framework supporting an FPGA backend device, and a related apparatus. The method includes: integrating an OpenCL standard API library into an nGraph framework; creating, in the nGraph framework, an FPGA backend device creation module for registering an FPGA rear-end device, initializing an OpenCL environment and acquiring the FPGA backend device; creating, in the nGraph framework, an FPGA buffer space processing module for opening up an FPGA buffer space and for reading and writing an FPGA cache; creating, in the nGraph framework, an OP kernel implementation module for creating an OP kernel and compiling the OP kernel; and creating, in the nGraph framework, an FPGA compiling execution module for registering, scheduling and executing the OP kernel.