公开(公告)号：US20230154522A1

公开(公告)日：2023-05-18

申请号：US17735542

申请日：2022-05-03

申请人： Samsung Electronics Co., Ltd.

发明人： Hijung KIM ,  Hoyoun KIM ,  Jungmin YOU ,  Seongjin CHO

IPC分类号： G11C11/406 ,  G11C11/408 ,  G11C11/4094 ,  G06F7/544

CPC分类号： G11C11/40622 ,  G11C11/40611 ,  G11C11/4085 ,  G11C11/4094 ,  G06F7/5443

摘要： A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a target row refresh logic circuit configured to select a target row address from among a plurality of target row addresses as a refresh row address based on victim point values, and perform a refresh operation on first memory cells of the plurality of memory cells connected to a wordline of the plurality of wordlines indicated by the refresh row address, a victim point table configured to store the victim point values for the target row addresses, and a victim point accumulator configured to receive a first row address from an external device, and accumulate a first victim point value for at least one target row address corresponding to the first row address during a unit time period.

公开(公告)号：US20230232614A1

公开(公告)日：2023-07-20

申请号：US18095041

申请日：2023-01-10

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Jaepil LEE ,  Hijung KIM

IPC分类号： H10B12/00

CPC分类号： H10B12/34 ,  H10B12/485 ,  H10B12/053

摘要： A semiconductor device includes a semiconductor substrate, an active region on the semiconductor substrate and including a first semiconductor material, an isolation layer on the semiconductor substrate and a side surface of the active region, a first gate structure in a first gate trench crossing the active region, a second gate structure in a second gate trench in the isolation layer, the second gate structure being parallel to the first gate structure and adjacent to the active region, a semiconductor layer covering at least a part of the side surface of the active region, the semiconductor layer including a second semiconductor material different from the first semiconductor material, and at least a part of the semiconductor layer being between the active region and the second gate structure, and source/drain regions in the active region on opposite sides of the first gate trench.

公开(公告)号：US20240233803A1

公开(公告)日：2024-07-11

申请号：US18613361

申请日：2024-03-22

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Hijung KIM ,  Hoyoun KIM ,  Jungmin YOU ,  Seongjin CHO

IPC分类号： G11C11/406 ,  G06F7/544 ,  G11C11/408 ,  G11C11/4094

CPC分类号： G11C11/40622 ,  G06F7/5443 ,  G11C11/40611 ,  G11C11/4085 ,  G11C11/4094

摘要： A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a target row refresh logic circuit configured to select a target row address from among a plurality of target row addresses as a refresh row address based on victim point values, and perform a refresh operation on first memory cells of the plurality of memory cells connected to a wordline of the plurality of wordlines indicated by the refresh row address, a victim point table configured to store the victim point values for the target row addresses, and a victim point accumulator configured to receive a first row address from an external device, and accumulate a first victim point value for at least one target row address corresponding to the first row address during a unit time period.

公开(公告)号：US20240185904A1

公开(公告)日：2024-06-06

申请号：US18232940

申请日：2023-08-11

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Hijung KIM ,  Seong-Jin CHO

IPC分类号： G11C11/406

CPC分类号： G11C11/406 ,  G11C2211/4062

摘要： A memory device includes a memory cell array including a plurality of rows, an ECC engine configured to determine a health level for each of the plurality of rows based on the number of corrections of errors of data read from each of the plurality of rows, a control logic configured to determine a victim row address based on the health level and the number of accesses for each of the plurality of rows, and a refresh control circuit configured to perform a refresh on a row corresponding to the determined victim row address.

公开(公告)号：US20240144990A1

公开(公告)日：2024-05-02

申请号：US18319655

申请日：2023-05-18

申请人： Samsung Electronics Co., Ltd.

发明人： Hijung KIM ,  Seongjin CHO

IPC分类号： G11C11/406 ,  G11C11/4078

CPC分类号： G11C11/40622 ,  G11C11/40611 ,  G11C11/4078

摘要： A memory device includes a memory cell array including a plurality of memory cells coupled to wordlines and bitlines, a target row refresh logic configured to perform a refresh operation based on a weighted access count on the memory cell array, a register configured to store a weighted access count for each of a plurality of row addresses; an accumulator configured to accumulate a current weighted access count corresponding to an access spacing to the weighted access count stored in the register, and a calculator configured to calculate the access spacing.

公开(公告)号：US20230223073A1

公开(公告)日：2023-07-13

申请号：US17953524

申请日：2022-09-27

申请人： SAMSUNG ELECTRONICS CO., LTD.

发明人： Hijung KIM ,  Jung Min YOU ,  Seong-Jin CHO

IPC分类号： G11C11/4096 ,  G11C11/408 ,  G11C17/16

CPC分类号： G11C11/4096 ,  G11C11/408 ,  G11C17/165

摘要： Disclosed is a memory device which includes a memory core that includes a plurality of memory cells, and control logic that receives a first active command and a first row address from an external device and activates memory cells corresponding to the first row address from among the plurality of memory cells in response to the first active command. The control logic includes registers and counters. The control logic records the first row address in one of the registers, counts an activation count of the first row address by using a first counter of the counters, and counts a lifetime count of the first row address by using a second counter of the counters.