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公开(公告)号：US20240233803A1
公开(公告)日：2024-07-11
申请号：US18613361
申请日：2024-03-22
发明人： Hijung KIM , Hoyoun KIM , Jungmin YOU , Seongjin CHO
IPC分类号： G11C11/406 , G06F7/544 , G11C11/408 , G11C11/4094
CPC分类号： G11C11/40622 , G06F7/5443 , G11C11/40611 , G11C11/4085 , G11C11/4094
摘要： A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a target row refresh logic circuit configured to select a target row address from among a plurality of target row addresses as a refresh row address based on victim point values, and perform a refresh operation on first memory cells of the plurality of memory cells connected to a wordline of the plurality of wordlines indicated by the refresh row address, a victim point table configured to store the victim point values for the target row addresses, and a victim point accumulator configured to receive a first row address from an external device, and accumulate a first victim point value for at least one target row address corresponding to the first row address during a unit time period.
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公开(公告)号：US20190302445A1
公开(公告)日：2019-10-03
申请号：US16367010
申请日：2019-03-27
发明人： Seongjin CHO , Naekyung KIM , Yongjoon KIM , Hanjun KIM , Jihyuk LIM
摘要： A wearable device includes at least one lens, an output device, at least one sensor, and at least one processor. The at least one processor is configured to identify a level of light sensed through the at least one sensor. The at least one processor is also configured to provide a notification related to the level of the light by using the output device when the level of the light satisfies a preset condition.
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公开(公告)号：US20230111467A1
公开(公告)日：2023-04-13
申请号：US17731994
申请日：2022-04-28
发明人： Seongjin CHO , Jungmin YOU
摘要： A semiconductor memory device includes a memory cell array including memory cell row, each of which includes volatile memory cells, a row hammer management circuit, a repair control circuit and a connection logic. The row hammer management circuit counts access addresses associated with the memory cell rows to store counting values, and determines a hammer address associated with least one of the memory cell rows, which is intensively accessed, based on the counting values. The repair control circuit includes repair controllers, each of which includes a defective address storage, and repairs a defective memory cell row among the memory cell rows. The connection logic connects first repair controllers, which are unused for storing defective addresses, among the plurality of repair controllers, to the row hammer management circuit. The row hammer management circuit uses the first repair controllers as a storage resource to store a portion of the access addresses.
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公开(公告)号：US20240361026A1
公开(公告)日：2024-10-31
申请号：US18767322
申请日：2024-07-09
发明人： Seongjin CHO
IPC分类号： F24F11/00 , F24F1/22 , F24F1/48 , F24F110/12 , F24F110/52 , F24F110/64
CPC分类号： F24F11/0001 , F24F1/22 , F24F1/48 , F24F2011/0002 , F24F2110/12 , F24F2110/52 , F24F2110/64
摘要： An air conditioner outdoor unit comprises: a cabinet including a heat exchanger, a compressor, and a fan; an internal cabinet provided inside the cabinet; a passage provided at a lower portion of the internal cabinet and in through which air flows; a vent provided at an upper portion of the internal cabinet and through which introduced air is discharged; an air guide duct disposed inside the internal cabinet; and a dust sensor disposed at the air guide duct and configured to detect dust concentration of the air passing through the internal cabinet.
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公开(公告)号：US20240144990A1
公开(公告)日：2024-05-02
申请号：US18319655
申请日：2023-05-18
发明人： Hijung KIM , Seongjin CHO
IPC分类号： G11C11/406 , G11C11/4078
CPC分类号： G11C11/40622 , G11C11/40611 , G11C11/4078
摘要： A memory device includes a memory cell array including a plurality of memory cells coupled to wordlines and bitlines, a target row refresh logic configured to perform a refresh operation based on a weighted access count on the memory cell array, a register configured to store a weighted access count for each of a plurality of row addresses; an accumulator configured to accumulate a current weighted access count corresponding to an access spacing to the weighted access count stored in the register, and a calculator configured to calculate the access spacing.
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公开(公告)号：US20230154522A1
公开(公告)日：2023-05-18
申请号：US17735542
申请日：2022-05-03
发明人： Hijung KIM , Hoyoun KIM , Jungmin YOU , Seongjin CHO
IPC分类号： G11C11/406 , G11C11/408 , G11C11/4094 , G06F7/544
CPC分类号： G11C11/40622 , G11C11/40611 , G11C11/4085 , G11C11/4094 , G06F7/5443
摘要： A memory device includes a memory cell array including a plurality of memory cells connected to a plurality of wordlines and a plurality of bitlines, a target row refresh logic circuit configured to select a target row address from among a plurality of target row addresses as a refresh row address based on victim point values, and perform a refresh operation on first memory cells of the plurality of memory cells connected to a wordline of the plurality of wordlines indicated by the refresh row address, a victim point table configured to store the victim point values for the target row addresses, and a victim point accumulator configured to receive a first row address from an external device, and accumulate a first victim point value for at least one target row address corresponding to the first row address during a unit time period.
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公开(公告)号：US20200293667A1
公开(公告)日：2020-09-17
申请号：US16815541
申请日：2020-03-11
发明人： Bumhan KIM , Sunjune KONG , Seongjin CHO
摘要： An electronic device including a secure Integrated Circuit (IC) is provided. The electronic device includes a secure IC configured as a System-on-Chip (SoC) and configured to provide a general environment and a security environment, wherein the secure IC includes a main processor configured to operate in the general environment, a secure processor configured to operate in the security environment and control security of data using a first security key, and a secure memory configured to be operatively connected to the secure processor and store a second security key corresponding to the first security key. Various other embodiments are possible.
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