公开(公告)号：US10140415B2

公开(公告)日：2018-11-27

申请号：US15407535

申请日：2017-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-eun Lee ,  Sung-hoon Kim ,  Jae-ick Son ,  Hyang-ja Yang

IPC: G06F17/50 ,  G11C16/04 ,  H01L27/115

Abstract: A method and system for verifying a layout of an integrated circuit (IC) is disclosed. The IC may include a plurality of strings each including a plurality of memory cells which are vertically stacked on a substrate. The method may include receiving schematic data of the IC including instances of a string symbol and layout data, preparing a layout versus schematic (LVS) rule file in which a string device is defined, and performing LVS verification.