公开(公告)号：US11923343B2

公开(公告)日：2024-03-05

申请号：US18059747

申请日：2022-11-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung Yoo ,  Jayeon Lee ,  Jae-eun Lee ,  Yeongkwon Ko ,  Jin-woo Park ,  Teak Hoon Lee

IPC: H01L25/065 ,  H01L23/13 ,  H01L23/31 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L23/13 ,  H01L23/3157 ,  H01L23/49822 ,  H01L23/49838 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2225/06586

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.

公开(公告)号：US11538792B2

公开(公告)日：2022-12-27

申请号：US17140241

申请日：2021-01-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaekyung Yoo ,  Jayeon Lee ,  Jae-eun Lee ,  Yeongkwon Ko ,  Jin-woo Park ,  Teak Hoon Lee

IPC: H01L25/065 ,  H01L23/31 ,  H01L23/13 ,  H01L23/498 ,  H01L25/00

Abstract: Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.

公开(公告)号：US10140415B2

公开(公告)日：2018-11-27

申请号：US15407535

申请日：2017-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-eun Lee ,  Sung-hoon Kim ,  Jae-ick Son ,  Hyang-ja Yang

IPC: G06F17/50 ,  G11C16/04 ,  H01L27/115

Abstract: A method and system for verifying a layout of an integrated circuit (IC) is disclosed. The IC may include a plurality of strings each including a plurality of memory cells which are vertically stacked on a substrate. The method may include receiving schematic data of the IC including instances of a string symbol and layout data, preparing a layout versus schematic (LVS) rule file in which a string device is defined, and performing LVS verification.