公开(公告)号：US20130043518A1

公开(公告)日：2013-02-21

申请号：US13633663

申请日：2012-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoonjoo NA ,  Sangjin HYUN ,  Yugyun SHIN ,  Hongbae PARK ,  Sughun HONG ,  Hye-Lan LEE ,  Hyung-Seok HONG

IPC: H01L29/78

CPC classification number: H01L21/823842 ,  H01L29/66545

Abstract: A method of fabricating a semiconductor device includes forming an interlayer dielectric on a substrate, the interlayer dielectric including first and second openings respectively disposed in first and second regions formed separately in the substrate; forming a first conductive layer filling the first and second openings; etching the first conductive layer such that a bottom surface of the first opening is exposed and a portion of the first conductive layer in the second opening remains; and forming a second conductive layer filling the first opening and a portion of the second opening.

Abstract translation: 制造半导体器件的方法包括在衬底上形成层间电介质，所述层间电介质包括分别设置在所述衬底中分开形成的第一和第二区域中的第一和第二开口; 形成填充所述第一和第二开口的第一导电层; 蚀刻第一导电层，使得第一开口的底表面露出，并且第二开口中的第一导电层的一部分保留; 以及形成填充所述第一开口和所述第二开口的一部分的第二导电层。