公开(公告)号：US20150294873A1

公开(公告)日：2015-10-15

申请号：US14636257

申请日：2015-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Huyong LEE ,  Jae-Jung KIM ,  Wandon KIM ,  Sangjin HYUN

IPC: H01L21/28 ,  H01L29/423 ,  H01L29/49 ,  H01L21/283

CPC classification number: H01L27/11521 ,  H01L29/40114 ,  H01L29/42336 ,  H01L29/66795 ,  H01L29/66825 ,  H01L29/785

Abstract: Provided is a method of fabricating a semiconductor device, including forming an interlayered insulating layer having an opening, on a substrate; sequentially forming a first conductive pattern, a barrier pattern, and a second conductive pattern on bottom and side surfaces of the opening; and nitrifying an upper portion of the second conductive pattern to form a metal nitride layer that is spaced apart from the first conductive pattern.

Abstract translation: 提供一种制造半导体器件的方法，包括在衬底上形成具有开口的层间绝缘层; 在开口的底部和侧表面上依次形成第一导电图案，阻挡图案和第二导电图案; 并且硝化第二导电图案的上部以形成与第一导电图案间隔开的金属氮化物层。

公开(公告)号：US20190198498A1

公开(公告)日：2019-06-27

申请号：US16116295

申请日：2018-08-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jongho PARK ,  Wandon KIM ,  Jeonghyuk YIM ,  Sangjin HYUN

IPC: H01L27/092 ,  H01L29/49 ,  H01L21/8238

Abstract: A semiconductor device includes first, second, and third transistors on a substrate and having different threshold voltages from each other, each of the first, second, and third transistors including: a gate insulating layer, a first work function metal layer, and a second work function metal layer. The first work function metal layer of the first transistor may include a first sub-work function layer, the first work function metal layer of the second transistor may include a second sub-work function layer, the first work function metal layer of the third transistor may include a third sub-work function layer, and the first, second, and third sub-work function layers may have different work functions from each other.

公开(公告)号：US20210335707A1

公开(公告)日：2021-10-28

申请号：US17367773

申请日：2021-07-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yuichiro SASAKI ,  Sungkeun LIM ,  Pil-Kyu KANG ,  Weonhong KIM ,  Seungha OH ,  Yongho HA ,  Sangjin HYUN

IPC: H01L23/522 ,  H01L23/50 ,  H01L23/528

Abstract: A semiconductor device includes a semiconductor layer having a first surface and a second surface opposite to the first surface, an active pattern on the first surface, the active pattern including a source/drain region, a power rail electrically connected to the source/drain region, and a power delivery network on the second surface, the power delivery network electrically connected to the power rail. The semiconductor layer includes an etch stop dopant, and the etch stop dopant has a maximum concentration at the second surface.

公开(公告)号：US20130043518A1

公开(公告)日：2013-02-21

申请号：US13633663

申请日：2012-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoonjoo NA ,  Sangjin HYUN ,  Yugyun SHIN ,  Hongbae PARK ,  Sughun HONG ,  Hye-Lan LEE ,  Hyung-Seok HONG

IPC: H01L29/78

CPC classification number: H01L21/823842 ,  H01L29/66545

Abstract: A method of fabricating a semiconductor device includes forming an interlayer dielectric on a substrate, the interlayer dielectric including first and second openings respectively disposed in first and second regions formed separately in the substrate; forming a first conductive layer filling the first and second openings; etching the first conductive layer such that a bottom surface of the first opening is exposed and a portion of the first conductive layer in the second opening remains; and forming a second conductive layer filling the first opening and a portion of the second opening.

Abstract translation: 制造半导体器件的方法包括在衬底上形成层间电介质，所述层间电介质包括分别设置在所述衬底中分开形成的第一和第二区域中的第一和第二开口; 形成填充所述第一和第二开口的第一导电层; 蚀刻第一导电层，使得第一开口的底表面露出，并且第二开口中的第一导电层的一部分保留; 以及形成填充所述第一开口和所述第二开口的一部分的第二导电层。

公开(公告)号：US20200381528A1

公开(公告)日：2020-12-03

申请号：US16998493

申请日：2020-08-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonkeun CHUNG ,  Heonbok LEE ,  Chunghwan SHIN ,  Yongsuk CHAI ,  Sangjin HYUN

IPC: H01L29/423 ,  H01L27/092 ,  H01L29/78 ,  H01L29/66 ,  H01L29/08

Abstract: A semiconductor device includes a substrate having an active pattern therein, a gate electrode extending across the active pattern and a source/drain region on the active pattern laterally adjacent the gate electrode. The device further includes a contact structure including a first contact on the source/drain region, a second contact on the first contact and a spacer on sidewalls of the first and second contacts.

公开(公告)号：US20200373331A1

公开(公告)日：2020-11-26

申请号：US16807410

申请日：2020-03-03

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Weonhong KIM ,  Pilkyu KANG ,  Yuichiro SASAKI ,  Sungkeun LIM ,  Yongho HA ,  Sangjin HYUN ,  Kughwan KIM ,  Seungha OH

IPC: H01L27/12 ,  H01L27/02 ,  H01L21/762

Abstract: An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.

公开(公告)号：US20170005175A1

公开(公告)日：2017-01-05

申请号：US15186982

申请日：2016-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaeyeol SONG ,  Wandon KIM ,  Hoonjoo NA ,  Suyoung BAE ,  Hyeok-Jun SON ,  Sangjin HYUN

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/78 ,  H01L27/085

CPC classification number: H01L29/517 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823462 ,  H01L27/085 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/518

Abstract: A semiconductor device includes a semiconductor substrate including multiple active regions having a common conductivity type and separate, respective gate electrodes on the separate active regions. Different high-k dielectric layers may he between the separate active regions and the respective gate electrodes on the active regions. Different quantities of high-k dielectric layers may be between the separate active regions and the respective gate electrodes on the active regions. The different high-k dielectric layers may include different work-function adjusting materials.

Abstract translation: 半导体器件包括半导体衬底，该半导体衬底包括具有共同导电类型的多个有源区和在分离的有源区上分开的相应的栅电极。 不同的高k电介质层可以在分离的有源区和有源区上的相应栅电极之间。 不同数量的高k电介质层可以在分离的有源区域和有源区域上的相应栅电极之间。 不同的高k电介质层可以包括不同的功函调整材料。

公开(公告)号：US20230361121A1

公开(公告)日：2023-11-09

申请号：US18353214

申请日：2023-07-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongsoo LEE ,  Wonkeun CHUNG ,  Hoonjoo NA ,  Suyoung BAE ,  Jaeyeol SONG ,  Jonghan LEE ,  HyungSuk JUNG ,  Sangjin HYUN

IPC: H01L27/092 ,  H01L29/786 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/51 ,  H01L29/423

CPC classification number: H01L27/0922 ,  H01L29/78696 ,  H01L21/823842 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/42392

Abstract: Disclosed are semiconductor devices and methods of manufacturing the same. The semiconductor device comprises a first transistor on a substrate, and a second transistor on the substrate. Each of the first and second transistors includes a plurality of semiconductor patterns vertically stacked on the substrate and vertically spaced apart from each other, and a gate dielectric pattern and a work function pattern filling a space between the semiconductor patterns. The work function pattern of the first transistor includes a first work function metal layer, the work function pattern of the second transistor includes the first work function metal layer and a second work function metal layer, the first work function metal layer of each of the first and second transistors has a work function greater than that of the second work function metal layer, and the first transistor has a threshold voltage less than that of the second transistor.

公开(公告)号：US20220231018A1

公开(公告)日：2022-07-21

申请号：US17712272

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghoon LEE ,  Jongho PARK ,  Wandon KIM ,  Sangjin HYUN

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/49 ,  H01L29/10 ,  H01L29/06

Abstract: A semiconductor device includes a plurality of semiconductor patterns that are sequentially stacked and spaced apart from each other on a substrate, and a gate electrode on the plurality of semiconductor patterns. The gate electrode includes a capping pattern and a work function pattern that are sequentially stacked on the plurality of semiconductor patterns. The capping pattern includes a first metal nitride layer including a first metal element, and a second metal nitride layer including a second metal element whose work function is greater than a work function of the first metal element. The first metal nitride layer is disposed between the second metal nitride layer and the plurality of semiconductor patterns. The first metal nitride layer is thinner than the second metal nitride layer.

公开(公告)号：US20220028895A1

公开(公告)日：2022-01-27

申请号：US17494275

申请日：2021-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Weonhong KIM ,  Pilkyu KANG ,  Yuichiro SASAKI ,  Sungkeun LIM ,  Yongho HA ,  Sangjin HYUN ,  Kughwan KIM ,  Seungha OH

IPC: H01L27/12 ,  H01L21/762 ,  H01L27/02

Abstract: An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.