公开(公告)号：US20250105154A1

公开(公告)日：2025-03-27

申请号：US18900133

申请日：2024-09-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Giyoung JO ,  Sangwon KIM ,  Jaewon KIM ,  Hyeon Jin SHIN ,  Van Luan NGUYEN ,  Chang Seok LEE

IPC: H01L23/532 ,  H01L21/768

Abstract: Disclosed is an interconnect structure including a substrate, a conductive layer on the substrate, and a passivation layer in contact with the conductive layer, where the passivation layer includes a first layer including boron nitride (h-BN) having a hexagonal crystal structure and a second layer including amorphous boron nitride (a-BN), and the first layer is in contact with the conductive layer the first layer.

公开(公告)号：US20220084952A1

公开(公告)日：2022-03-17

申请号：US17379000

申请日：2021-07-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang Eun LEE ,  Min Joo LEE ,  Wan Don KIM ,  Hyeon Jin SHIN ,  Hyun Bae LEE ,  Hyun Seok LIM

IPC: H01L23/532

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate including an element isolation layer, the element isolation layer defining an active region, a plurality of word lines traversing the active region in a first direction, and a plurality of bit line structures on the substrate and connected to the active region, the plurality of bit line structures extending in a second direction different from the first direction. Each of the plurality of bit line structures includes a ruthenium line wiring including a bottom surface and a top surface opposite to the bottom surface, a lower graphene layer in contact with the bottom surface of the ruthenium line wiring and extending along the bottom surface of the ruthenium line wiring, and a wiring line capping layer extending along the top surface of the ruthenium line wiring.