公开(公告)号：US20210343669A1

公开(公告)日：2021-11-04

申请号：US17158450

申请日：2021-01-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Uidam JUNG ,  Hyoungyol MUN ,  Sangjun PARK ,  Kyuha LEE

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor device includes a first structure including a first bonding structure, and a second structure on the first structure and including a second bonding structure connected to the first bonding structure. The first bonding structure includes a first insulating layer, a first bonding insulating layer on the first insulating layer, first bonding pads penetrating at least a portion of the first insulating layer and the first bonding insulating layer, and first metal patterns in the first insulating layer and in contact with the first bonding insulating layer, and having an upper surface at a lower level than upper surfaces of the first bonding pads. The second bonding structure includes a second bonding insulating layer bonded to the first bonding insulating layer, a second insulating layer on the second bonding insulating layer, and second bonding pads penetrating the second bonding insulating layer and connected to the first bonding pads.

公开(公告)号：US20230019790A1

公开(公告)日：2023-01-19

申请号：US17742619

申请日：2022-05-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsung KANG ,  Hyoungyol MUN ,  Sungdong CHO ,  Wonhee CHO

IPC: H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device includes a semiconductor substrate including a first region and a second region, first metal lines spaced apart from each other at a first interval on the first region, second metal lines spaced apart from each other at a second interval on the second region, the second interval being less than the first interval, and a passivation layer on the semiconductor substrate and covering the first and second metal lines, the passivation layer including sidewall parts covering sidewalls of the first metal lines and the second metal lines, the sidewall parts including a porous dielectric layer, upper parts covering top surfaces of the first metal lines and the second metal lines, and an air gap defined by the sidewall parts between the second metal lines.

公开(公告)号：US20220139806A1

公开(公告)日：2022-05-05

申请号：US17371602

申请日：2021-07-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangwuk PARK ,  Youngmin LEE ,  Hyoungyol MUN ,  Inyoung LEE ,  Seokhwan JEONG ,  Sungdong CHO

IPC: H01L23/48 ,  H01L25/065 ,  H01L23/528 ,  H01L21/768

Abstract: A semiconductor device, includes: a substrate having a first surface on which a plurality of devices are disposed and a second surface, opposite to the first surface; an interlayer insulating film on the first surface of the substrate; an etching delay layer disposed in a region between the substrate and the interlayer insulating film; first and second landing pads on the interlayer insulating film; a first through electrode penetrating through the substrate and the interlayer insulating film; and a second through electrode penetrating the substrate, the etching delay layer, and the interlayer insulating film, the second through electrode having a width, greater than that of the first through electrode, wherein each of the first and second through electrodes includes first and second tapered end portions in the interlayer insulating film, each of first and second tapered end portions having a cross-sectional shape narrowing closer to the landing pads.

公开(公告)号：US20220020667A1

公开(公告)日：2022-01-20

申请号：US17213767

申请日：2021-03-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwangwuk PARK ,  Youngmin LEE ,  Sungdong CHO ,  Eunji KIM ,  Hyoungyol MUN ,  Seokhwan JEONG

IPC: H01L23/48 ,  H01L21/762

Abstract: A semiconductor includes a substrate having a first surface and a second surface opposite to each other, the substrate having a via hole extending in a thickness direction from the first surface, a circuit pattern in the first surface of the substrate, a through electrode structure in the via hole, a device isolation structure in a first trench extending in one direction in the first surface of the substrate, the device isolation structure between the via hole and the circuit pattern, the device isolation structure including a first oxide layer pattern and a first nitride layer pattern sequentially stacked on an inner surface of the first trench, the first nitride layer pattern filling the first trench, and an insulation interlayer on the first surface of the substrate and covering the circuit pattern.