公开(公告)号：US20170092344A1

公开(公告)日：2017-03-30

申请号：US15264946

申请日：2016-09-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kwan Yeob CHAE ,  Hyun-Hyuck KIM ,  Sang Hune PARK ,  Shin Young YI ,  Won LEE

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G06F13/4243 ,  G11C7/22

Abstract: A data processing circuit includes a delay circuit configured to delay a data signal and generate delayed data signals each having a different delay; and an output control circuit configured to output a first data signal among the delayed data signals as a data signal sampled at a first edge of a sampling clock signal, and output a second data signal among the delayed data signals as a data signal sampled at a second edge of the sampling clock signal.