公开(公告)号：US20210305114A1

公开(公告)日：2021-09-30

申请号：US17087879

申请日：2020-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： CHANHO LEE ,  WON KIM ,  HAESEOK PARK ,  ILGEUN JUNG ,  JINKUK BAE ,  INYOUNG LEE ,  SUNGDONG CHO

IPC: H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package may include a base, a first chip on the base, and first connection patterns that connect and couple the base and the first chip. The first chip may include a substrate, pad patterns on the substrate, a passivation layer on the substrate and having openings, and pillars on the substrate, the pad patterns include a first signal pad and a second signal pad, the first connection patterns are in contact with the pillars, the pillars include a first signal pillar in contact with the first signal pad and a second signal pillar in contact with the second signal pad, the openings in the passivation layer include a first opening having a sidewall facing a side surface of the first signal pillar and surrounding the side surface of the first signal pillar, and a second opening having a sidewall facing a side surface of the second signal pillar and surrounding the side surface of the second signal pillar, and a maximum width of the second opening is greater than a maximum width of the first opening.