公开(公告)号：US20240215229A1

公开(公告)日：2024-06-27

申请号：US18224546

申请日：2023-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： MINSUNG KANG ,  WONHEE CHO ,  HYOUNGYOL MUN ,  SUNGDONG CHO

IPC: H10B12/00

CPC classification number: H10B12/50 ,  H10B12/01 ,  H10B12/315

Abstract: A semiconductor device may include a semiconductor layer on a substrate, a first insulating layer on the semiconductor layer, a first conductive structure, which is provided to penetrate the first insulating layer in a vertical direction perpendicular to a bottom surface of the substrate and is connected to the semiconductor layer, a second insulating layer covering the first insulating layer and the first conductive structure, a second conductive structure, which is provided to penetrate the second insulating layer in the vertical direction and is connected to the first conductive structure, and a diffusion barrier layer covering a top surface of the first insulating layer and extending to a side surface of the first conductive structure. The lowermost surface of the second conductive structure may be located at a height higher than the top surface of the first insulating layer.

公开(公告)号：US20210305114A1

公开(公告)日：2021-09-30

申请号：US17087879

申请日：2020-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： CHANHO LEE ,  WON KIM ,  HAESEOK PARK ,  ILGEUN JUNG ,  JINKUK BAE ,  INYOUNG LEE ,  SUNGDONG CHO

IPC: H01L23/31 ,  H01L23/00 ,  H01L25/065 ,  H01L25/18

Abstract: A semiconductor package may include a base, a first chip on the base, and first connection patterns that connect and couple the base and the first chip. The first chip may include a substrate, pad patterns on the substrate, a passivation layer on the substrate and having openings, and pillars on the substrate, the pad patterns include a first signal pad and a second signal pad, the first connection patterns are in contact with the pillars, the pillars include a first signal pillar in contact with the first signal pad and a second signal pillar in contact with the second signal pad, the openings in the passivation layer include a first opening having a sidewall facing a side surface of the first signal pillar and surrounding the side surface of the first signal pillar, and a second opening having a sidewall facing a side surface of the second signal pillar and surrounding the side surface of the second signal pillar, and a maximum width of the second opening is greater than a maximum width of the first opening.

公开(公告)号：US20210020545A1

公开(公告)日：2021-01-21

申请号：US16932726

申请日：2020-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： EUNJI KIM ,  SUNGDONG CHO ,  KWANGWUK PARK ,  SANGJUN PARK ,  DAESUK LEE ,  HAKSEUNG LEE

IPC: H01L23/48 ,  H01L21/768 ,  H01L25/18

Abstract: A semiconductor device includes a semiconductor substrate having an active surface on which semiconductor elements are provided. An interlayer insulating film is provided on the semiconductor substrate. A first via structure passes through the semiconductor substrate. The first via structure has a first diameter. A second via structure passes through the semiconductor substrate. The second via structure has a second diameter that is greater than the first diameter. The first via structure has a step portion that is in contact with the interlayer insulating film.