公开(公告)号：US20140286359A1

公开(公告)日：2014-09-25

申请号：US14152297

申请日：2014-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo-Hyun DO ,  In-Hyoung KIM

IPC: H04L7/00

CPC classification number: H04L27/2657 ,  H04L5/001 ,  H04L2027/0065

Abstract: A circuit for processing Carrier Aggregation (CA) is provided. The circuit includes a plurality of Component Carrier (CC) processors, each CC processor configured to estimate a frequency offset for a related CC and to compensate the estimated frequency offset, a reference clock generator configured to generate a reference clock using a reference frequency offset as one of frequency offsets output from the plurality of CC processors, a plurality of reception Phase Lock Loop (PLL) units, each reception PLL unit configured to generate a reception carrier frequency for the related CC corresponding to the reference clock, and a plurality of transmission PLL units, each transmission PLL unit configured to generate a transmission carrier frequency for the related CC corresponding to the reference clock.

Abstract translation: 提供了一种用于处理载波聚合（CA）的电路。 所述电路包括多个分量载波（CC）处理器，每个CC处理器被配置为估计相关CC的频率偏移并补偿所估计的频率偏移;参考时钟发生器，被配置为使用参考频率偏移生成参考时钟 从多个CC处理器输出的频率偏移中的一个，多个接收锁相环（PLL）单元，每个接收PLL单元被配置为产生对应于参考时钟的相关CC的接收载波频率，以及多个传输 PLL单元，每个传输PLL单元被配置为产生对应于参考时钟的相关CC的传输载波频率。

公开(公告)号：US20180035316A1

公开(公告)日：2018-02-01

申请号：US15582901

申请日：2017-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Sik KIM ,  Hui-Won JE ,  In-Hyoung KIM ,  Se-Bin IM ,  Young-Seok JUNG

IPC: H04W24/02 ,  H04L5/00 ,  H04L27/26 ,  H04L1/20

CPC classification number: H04W24/02 ,  H04J11/005 ,  H04L1/20 ,  H04L5/0035 ,  H04L5/0048 ,  H04L5/005 ,  H04L5/0053 ,  H04L5/0073 ,  H04L27/265

Abstract: A chipset including at least one processor is provided. The at least one processor of the chipset is configured to acquire an interference whitening (IW) and detection scheme and demodulate an interference signal based on the acquired IW and detection scheme, wherein the IW and detection scheme is determined based on an interference characteristic of the interference signal, and the interference characteristic is determined based on whether a region in which the interference signal is included collides with a reference signal region of a serving cell and whether the interference signal is a reference signal.

公开(公告)号：US20160050098A1

公开(公告)日：2016-02-18

申请号：US14922798

申请日：2015-10-26

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joo-Hyun DO ,  In-Hyoung KIM

IPC: H04L27/26 ,  H04L5/00

CPC classification number: H04L27/2657 ,  H04L5/001 ,  H04L2027/0065

Abstract: A circuit for processing Carrier Aggregation (CA) is provided. The circuit includes a plurality of Component Carrier (CC) processors, each CC processor configured to estimate a frequency offset for a related CC and to compensate the estimated frequency offset, a reference clock generator configured to generate a reference clock using a reference frequency offset as one of frequency offsets output from the plurality of CC processors, a plurality of reception Phase Lock Loop (PLL) units, each reception PLL unit configured to generate a reception carrier frequency for the related CC corresponding to the reference clock, and a plurality of transmission PLL units, each transmission PLL unit configured to generate a transmission carrier frequency for the related CC corresponding to the reference clock.

Abstract translation: 提供了一种用于处理载波聚合（CA）的电路。 所述电路包括多个分量载波（CC）处理器，每个CC处理器被配置为估计相关CC的频率偏移并补偿所估计的频率偏移;参考时钟发生器，被配置为使用参考频率偏移生成参考时钟 从多个CC处理器输出的频率偏移中的一个，多个接收锁相环（PLL）单元，每个接收PLL单元被配置为产生对应于参考时钟的相关CC的接收载波频率，以及多个传输 PLL单元，每个传输PLL单元被配置为产生对应于参考时钟的相关CC的传输载波频率。