公开(公告)号：US20170301381A1

公开(公告)日：2017-10-19

申请号：US15436234

申请日：2017-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun SEOMUN ,  Insub Shin ,  Kyungtae Do ,  JungYun Choi

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1012 ,  G11C5/143 ,  G11C7/10 ,  G11C7/222

Abstract: Voltage monitors include a predelay cell having an input responsive to a first clock signal. This cell is configured to generate a predelayed clock signal at an output thereof. A serially-connected string of data delay cells is provided, which has an input responsive to the predelayed clock signal. A serially-connected string of clock delay cells is provided, which has an input responsive to a second clock signal that is synchronized to the first clock signal. A plurality latches are provided. The latches have respective data inputs, which are responsive to first periodic signals generated at respective outputs of the serially-connected string of data delay cells, and respective clock/sync terminals, which are responsive to second periodic signals generated at respective outputs of the serially-connected string of clock delay cells. The latches enable loading of a delay code value, which indicates power supply voltage variation.

公开(公告)号：US09984732B2

公开(公告)日：2018-05-29

申请号：US15436234

申请日：2017-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jun Seomun ,  Insub Shin ,  Kyungtae Do ,  JungYun Choi

IPC: G11C7/22 ,  G11C7/10

CPC classification number: G11C7/1012 ,  G11C5/143 ,  G11C7/10 ,  G11C7/222

Abstract: Voltage monitors include a predelay cell having an input responsive to a first clock signal. This cell is configured to generate a predelayed clock signal at an output thereof. A serially-connected string of data delay cells is provided, which has an input responsive to the predelayed clock signal. A serially-connected string of clock delay cells is provided, which has an input responsive to a second clock signal that is synchronized to the first clock signal. A plurality latches are provided. The latches have respective data inputs, which are responsive to first periodic signals generated at respective outputs of the serially-connected string of data delay cells, and respective clock/sync terminals, which are responsive to second periodic signals generated at respective outputs of the serially-connected string of clock delay cells. The latches enable loading of a delay code value, which indicates power supply voltage variation.