公开(公告)号：US20210143102A1

公开(公告)日：2021-05-13

申请号：US16922163

申请日：2020-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YEONGKWON KO ,  JAEEUN LEE ,  JUNYEONG HEO

IPC: H01L23/538 ,  H01L25/065

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, a plurality of semiconductor elements disposed on the first surface in a device region, an insulating protective layer, and a connection pad. The second surface is divided into a first region overlapping the device region, and a second region surrounding the first region. The insulating protective layer is disposed on the second surface of the semiconductor substrate, and includes an edge pattern positioned in the second region. The edge pattern includes a thinner portion having a thickness smaller than a thickness of a center portion of the insulating protective layer positioned in the first region and/or an open region exposing the second surface of the semiconductor substrate. The connection pad is disposed on the center portion of the insulating protective layer and is electrically connected to the semiconductor elements.

公开(公告)号：US20230326863A1

公开(公告)日：2023-10-12

申请号：US18328322

申请日：2023-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YEONGKWON KO ,  JAEEUN LEE ,  JUNYEONG HEO

IPC: H01L23/538 ,  H01L25/065

CPC classification number: H01L23/5385 ,  H01L23/5386 ,  H01L25/0657

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, a plurality of semiconductor elements disposed on the first surface in a device region, an insulating protective layer, and a connection pad. The second surface is divided into a first region overlapping the device region, and a second region surrounding the first region. The insulating protective layer is disposed on the second surface of the semiconductor substrate, and includes an edge pattern positioned in the second region. The edge pattern includes a thinner portion having a thickness smaller than a thickness of a center portion of the insulating protective layer positioned in the first region and/or an open region exposing the second surface of the semiconductor substrate. The connection pad is disposed on the center portion of the insulating protective layer and is electrically connected to the semiconductor elements.

公开(公告)号：US20220157731A1

公开(公告)日：2022-05-19

申请号：US17589301

申请日：2022-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YEONGKWON KO ,  JAEEUN LEE ,  JUNYEONG HEO

IPC: H01L23/538 ,  H01L25/065

Abstract: A semiconductor device includes a semiconductor substrate having a first surface and a second surface opposing each other, a plurality of semiconductor elements disposed on the first surface in a device region, an insulating protective layer, and a connection pad. The second surface is divided into a first region overlapping the device region, and a second region surrounding the first region. The insulating protective layer is disposed on the second surface of the semiconductor substrate, and includes an edge pattern positioned in the second region. The edge pattern includes a thinner portion having a thickness smaller than a thickness of a center portion of the insulating protective layer positioned in the first region and/or an open region exposing the second surface of the semiconductor substrate. The connection pad is disposed on the center portion of the insulating protective layer and is electrically connected to the semiconductor elements.

公开(公告)号：US20210028098A1

公开(公告)日：2021-01-28

申请号：US16787107

申请日：2020-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAEKYUNG YOO ,  JAEEUN LEE ,  YEONGKWON KO ,  TEAKHOON LEE

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/18 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56

Abstract: Semiconductor packages may include a semiconductor chip including a chip pad and a lower redistribution that includes a lower redistribution insulating layer and a lower redistribution pattern. The lower redistribution insulating layer may include a top surface facing the semiconductor chip. The semiconductor packages may also include a molding layer on a side of the semiconductor chip and including a bottom surface facing the lower redistribution structure and a conductive post in the molding layer. The conductive post may include a bottom surface contacting the lower redistribution. The top surface of the lower redistribution insulating layer may be closer to a top surface of the conductive post than a top surface of the molding layer. A roughness of the top surface of the molding layer may be greater than a roughness of the top surface of the conductive post.