公开(公告)号：US20220293563A1

公开(公告)日：2022-09-15

申请号：US17405130

申请日：2021-08-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YEONGKWON KO ,  JINWOO PARK ,  JAEKYUNG YOO ,  TEAKHOON LEE

IPC: H01L25/065 ,  H01L21/56 ,  H01L25/00 ,  H01L23/00

Abstract: A semiconductor package includes a package substrate on which a base chip is disposed. A first semiconductor chip is disposed on the base chip. A second semiconductor chip is disposed on the first semiconductor chip. An inner mold layer surrounds an upper surface of the base chip and respective side surfaces of the first semiconductor chip and the second semiconductor chip. A first outer mold layer is interposed between the package substrate and the base chip while covering at least a portion of a side surface of the base chip. A second outer mold layer is disposed on the first outer mold layer while covering at least a portion of a side surface of the inner mold layer. The second outer mold layer is spaced apart from the package substrate. The first outer mold layer and the second outer mold layer have different viscosities.

公开(公告)号：US20210028098A1

公开(公告)日：2021-01-28

申请号：US16787107

申请日：2020-02-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： JAEKYUNG YOO ,  JAEEUN LEE ,  YEONGKWON KO ,  TEAKHOON LEE

IPC: H01L23/498 ,  H01L23/31 ,  H01L23/00 ,  H01L25/18 ,  H01L21/48 ,  H01L25/00 ,  H01L21/56

Abstract: Semiconductor packages may include a semiconductor chip including a chip pad and a lower redistribution that includes a lower redistribution insulating layer and a lower redistribution pattern. The lower redistribution insulating layer may include a top surface facing the semiconductor chip. The semiconductor packages may also include a molding layer on a side of the semiconductor chip and including a bottom surface facing the lower redistribution structure and a conductive post in the molding layer. The conductive post may include a bottom surface contacting the lower redistribution. The top surface of the lower redistribution insulating layer may be closer to a top surface of the conductive post than a top surface of the molding layer. A roughness of the top surface of the molding layer may be greater than a roughness of the top surface of the conductive post.

公开(公告)号：US20230048729A1

公开(公告)日：2023-02-16

申请号：US17707007

申请日：2022-03-29

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YEONGKWON KO ,  UNBYOUNG KANG ,  SOYEON KWON ,  YOONSUNG KIM ,  TEAKHOON LEE

IPC: H01L23/00 ,  H01L23/544

Abstract: A semiconductor package and a method of forming the same are provided. The semiconductor package includes: a semiconductor substrate having a front side and a back side, the semiconductor substrate having a chip area and a dummy area; a front structure below the front side, and including an internal circuit, an internal connection pattern, a guard pattern, and a front insulating structure; a rear protective layer overlapping the chip area and the dummy area, and a rear protrusion pattern on the rear protective layer and overlapping the dummy area, the rear protective layer and the rear protrusion pattern being on the back side; a through-electrode structure penetrating through the chip area and the rear protective layer, and electrically connected to the internal connection pattern; and a rear pad electrically connected to the through-electrode structure. The internal circuit and the internal connection pattern are below the chip area, and the guard pattern is below the chip area adjacent to the dummy area.