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    METHODS OF PERFORMING MULTIPLE DATA BUS INVERSION (DBI) AND MEMORY DEVICES PERFORMING THE METHODS
    1.
    发明申请
    METHODS OF PERFORMING MULTIPLE DATA BUS INVERSION (DBI) AND MEMORY DEVICES PERFORMING THE METHODS 审中-公开

    公开(公告)号：US20190129877A1

    公开(公告)日：2019-05-02

    申请号：US15969797

    申请日：2018-05-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byung-Kyu Ho ,  Jae-Woong Lee

    IPC: G06F13/36 ,  G06F9/445

    Abstract: A method of performing multiple data bus inversion (DBI) and a memory device performing the method are provided. The multiple DBI includes first through third DBI operations, wherein the first DBI operation determines whether to perform data inversion on a first data inversion group in which M×N data bits of a M×N data bit structure are grouped and performs the data inversion on the first data inversion group, the second DBI operation determines whether to perform data inversion on second data inversion groups formed by grouping M data bits from among the M×N data bits and performs the data inversion on the second data inversion groups, and the third DBI operation determines whether to perform data inversion on third data inversion groups formed by grouping N data bits from among the M×N data bits and performs the data inversion on the third data inversion groups.

    Methods of performing multiple data bus inversion (DBI) and memory devices performing the methods
    2.
    发明授权
    Methods of performing multiple data bus inversion (DBI) and memory devices performing the methods 有权

    公开(公告)号：US10747695B2

    公开(公告)日：2020-08-18

    申请号：US15969797

    申请日：2018-05-03

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Byung-Kyu Ho ,  Jae-Woong Lee

    IPC: G11C7/10 ,  H04L25/49 ,  G06F13/36 ,  G06F9/445

    Abstract: A method of performing multiple data bus inversion (DBI) and a memory device performing the method are provided. The multiple DBI includes first through third DBI operations, wherein the first DBI operation determines whether to perform data inversion on a first data inversion group in which M×N data bits of a M×N data bit structure are grouped and performs the data inversion on the first data inversion group, the second DBI operation determines whether to perform data inversion on second data inversion groups formed by grouping M data bits from among the M×N data bits and performs the data inversion on the second data inversion groups, and the third DBI operation determines whether to perform data inversion on third data inversion groups formed by grouping N data bits from among the M×N data bits and performs the data inversion on the third data inversion groups.

    Volatile memory device and memory controller
    4.
    发明授权
    Volatile memory device and memory controller 有权
    易失性存储器件和存储器控制器

    公开(公告)号：US09015389B2

    公开(公告)日：2015-04-21

    申请号：US14031897

    申请日：2013-09-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-Woong Lee ,  Hyong-Ryol Hwang

    IPC: G06F3/00 ,  G06F13/12 ,  G06F13/38 ,  G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C11/406

    CPC classification number: G11C11/40615

    Abstract: A volatile memory device includes a memory cell array, a command decoder, a self-refresh circuit, and a register. The command decoder is configured to decode a self-refresh entry command, a self-refresh exit command, and a register read command based on external command signals received from outside the volatile memory device. The self-refresh circuit is configured to automatically refresh the memory cell array during a self-refresh mode which be entered in response to the self-refresh entry command and be exited in response to the self-refresh exit command. The register is configured to store an accessible state in response to the self-refresh exit command, and output the stored accessible state in response to the register read command. The accessible state indicates whether or not the memory cell array is ready to be read or written.

    Abstract translation: 易失性存储器件包括存储单元阵列，命令解码器，自刷新电路和寄存器。 命令解码器被配置为基于从易失性存储器设备外部接收的外部命令信号来解码自刷新输入命令，自刷新退出命令和寄存器读取命令。 自刷新电路被配置为在自刷新模式期间自动刷新存储单元阵列，该自刷新模式响应于自刷新输入命令被输入，并且响应于自刷新退出命令被退出。 寄存器被配置为响应于自刷新退出命令来存储可访问状态，并且响应于寄存器读取命令输出存储的可访问状态。 可访问状态指示存储单元阵列是否准备好被读取或写入。

    Method and terminal for implementing communication
    5.
    发明授权
    Method and terminal for implementing communication 有权

    公开(公告)号：US12167301B2

    公开(公告)日：2024-12-10

    申请号：US17725191

    申请日：2022-04-20

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Yun-Sun Baek ,  Nishant Gupta ,  Kill-Yeon Kim ,  Duk-Gu Sung ,  Jae-Woong Lee

    IPC: H04W4/10 ,  H04L65/403 ,  H04L65/4061 ,  H04W4/08 ,  H04W76/45 ,  H04W76/50 ,  H04W84/18

    Abstract: Provided is a method performed by a terminal of performing communication, the method including generating a private call setup request message including a call identifier information element (IE), a caller IE, a callee IE, and a call type IE set to an emergency private call, based on receiving a user indication to upgrade a call to emergency call, wherein the terminal is in an in-progress private call state; setting a proximity-based services (ProSe) per-packet priority corresponding to the emergency private call; transmitting, to another terminal, the private call setup request message; starting a timer relating to private call request retransmission based on the emergency call setup request message; and entering an in-progress emergency private call state from the in-progress private call state.

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