公开(公告)号：US10762947B2

公开(公告)日：2020-09-01

申请号：US16388961

申请日：2019-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Keon Lee ,  Kyung-Soo Ha ,  Hyong-Ryol Hwang

IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  H01L25/065 ,  G06F11/10 ,  G11C29/52 ,  H01L25/18

Abstract: A memory device is provided. The memory device receives a main clock signal and provides an internal main clock signal; a data clock buffer to receive a data clock signal; and a latency control circuit configured to generate latency information based on the data clock signal and provide the latency information to a data circuit. The latency control circuit includes: a divider configured to generate divided-by-two clock signals based on the data clock signal; a divider configured to generate divided-by-four clock signals based on a first group of the divided-by-two clock signals; a first synchronization detector configured to output divided-by-two alignment signals indicating whether a second group of divided-by-two clock signals is synchronized with the data clock signal; and a latency selector configured to detect phases of the divided-by-four clock signals based on the divided-by-two alignment signals and adjust a latency of the main clock signal based on the phases.

公开(公告)号：US20200111523A1

公开(公告)日：2020-04-09

申请号：US16388961

申请日：2019-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Keon LEE ,  Kyung-Soo Ha ,  Hyong-Ryol Hwang

IPC: G11C11/4076 ,  G11C11/408 ,  G11C11/4096 ,  H01L25/065 ,  H01L25/18 ,  G06F11/10 ,  G11C29/52

Abstract: A memory device is provided. The memory device receives a main clock signal and provides an internal main clock signal; a data clock buffer to receive a data clock signal; and a latency control circuit configured to generate latency information based on the data clock signal and provide the latency information to a data circuit. The latency control circuit includes: a divider configured to generate divided-by-two clock signals based on the data clock signal; a divider configured to generate divided-by-four clock signals based on a first group of the divided-by-two clock signals; a first synchronization detector configured to output divided-by-two alignment signals indicating whether a second group of divided-by-two clock signals is synchronized with the data clock signal; and a latency selector configured to detect phases of the divided-by-four clock signals based on the divided-by-two alignment signals and adjust a latency of the main clock signal based on the phases.

公开(公告)号：US11327838B2

公开(公告)日：2022-05-10

申请号：US16389080

申请日：2019-04-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jung-Hwan Park ,  Tae-Young Oh ,  Hyung-Joon Chi ,  Kyung-Soo Ha ,  Hyong-Ryol Hwang

IPC: G06F11/10 ,  G11C7/22

Abstract: A memory device includes: a first memory bank and a second memory bank; a control logic configured to receive a command and control an internal operation of the memory device; and an error correction code (ECC) circuit configured to retain in a latch circuit first read data read from the first memory bank in response to a first masked write (MWR) command for the first memory bank based on a latch control signal from the control logic, generate a first parity from data in which the first read data retained in the latch circuit is merged with first write data corresponding to the first MWR command in response to a first write control signal received from the control logic, and control an ECC operation to retain in the latch circuit second read data read from the second memory bank based on the latch control signal.

公开(公告)号：US09015389B2

公开(公告)日：2015-04-21

申请号：US14031897

申请日：2013-09-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-Woong Lee ,  Hyong-Ryol Hwang

IPC: G06F3/00 ,  G06F13/12 ,  G06F13/38 ,  G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G11C11/406

CPC classification number: G11C11/40615

Abstract: A volatile memory device includes a memory cell array, a command decoder, a self-refresh circuit, and a register. The command decoder is configured to decode a self-refresh entry command, a self-refresh exit command, and a register read command based on external command signals received from outside the volatile memory device. The self-refresh circuit is configured to automatically refresh the memory cell array during a self-refresh mode which be entered in response to the self-refresh entry command and be exited in response to the self-refresh exit command. The register is configured to store an accessible state in response to the self-refresh exit command, and output the stored accessible state in response to the register read command. The accessible state indicates whether or not the memory cell array is ready to be read or written.

Abstract translation: 易失性存储器件包括存储单元阵列，命令解码器，自刷新电路和寄存器。 命令解码器被配置为基于从易失性存储器设备外部接收的外部命令信号来解码自刷新输入命令，自刷新退出命令和寄存器读取命令。 自刷新电路被配置为在自刷新模式期间自动刷新存储单元阵列，该自刷新模式响应于自刷新输入命令被输入，并且响应于自刷新退出命令被退出。 寄存器被配置为响应于自刷新退出命令来存储可访问状态，并且响应于寄存器读取命令输出存储的可访问状态。 可访问状态指示存储单元阵列是否准备好被读取或写入。