公开(公告)号：US10510724B2

公开(公告)日：2019-12-17

申请号：US15832266

申请日：2017-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-kyung Yoo ,  Jin-woo Park

IPC: H01L23/02 ,  H01L25/065 ,  H01L21/66 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56

Abstract: A semiconductor device package includes a buffer layer having an upper surface perpendicular to a first direction, a plurality of semiconductor chips stacked on the buffer layer one by one in the first direction, and a chip sealing material surrounding sidewalls of the semiconductor chips. The semiconductor chips include an upper semiconductor chip at a farthest position from the buffer layer and a remaining plurality of intermediate semiconductor chips. Each of the intermediate semiconductor chips includes through silicon vias (TSVs) passing through each of the intermediate semiconductor chips. The upper semiconductor chip includes a trench formed in at least a portion of a periphery of the upper semiconductor chip and covered by the chip sealing material. Accordingly, the semiconductor device package provides increased device reliability.

公开(公告)号：US20190043831A1

公开(公告)日：2019-02-07

申请号：US15832266

申请日：2017-12-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae-kyung Yoo ,  Jin-woo Park

IPC: H01L25/065 ,  H01L21/66 ,  H01L23/538 ,  H01L23/00 ,  H01L23/31

Abstract: A semiconductor device package includes a buffer layer having an upper surface perpendicular to a first direction, a plurality of semiconductor chips stacked on the buffer layer one by one in the first direction, and a chip sealing material surrounding sidewalls of the semiconductor chips. The semiconductor chips include an upper semiconductor chip at a farthest position from the buffer layer and a remaining plurality of intermediate semiconductor chips. Each of the intermediate semiconductor chips includes through silicon vias (TSVs) passing through each of the intermediate semiconductor chips. The upper semiconductor chip includes a trench formed in at least a portion of a periphery of the upper semiconductor chip and covered by the chip sealing material. Accordingly, the semiconductor device package provides increased device reliability.