中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

18 records (took 0.019 seconds)

    Semiconductor device package
    3.
    发明授权
    Semiconductor device package 有权

    公开(公告)号：US10510724B2

    公开(公告)日：2019-12-17

    申请号：US15832266

    申请日：2017-12-05

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jae-kyung Yoo ,  Jin-woo Park

    IPC: H01L23/02 ,  H01L25/065 ,  H01L21/66 ,  H01L23/31 ,  H01L23/00 ,  H01L23/538 ,  H01L25/00 ,  H01L21/56

    Abstract: A semiconductor device package includes a buffer layer having an upper surface perpendicular to a first direction, a plurality of semiconductor chips stacked on the buffer layer one by one in the first direction, and a chip sealing material surrounding sidewalls of the semiconductor chips. The semiconductor chips include an upper semiconductor chip at a farthest position from the buffer layer and a remaining plurality of intermediate semiconductor chips. Each of the intermediate semiconductor chips includes through silicon vias (TSVs) passing through each of the intermediate semiconductor chips. The upper semiconductor chip includes a trench formed in at least a portion of a periphery of the upper semiconductor chip and covered by the chip sealing material. Accordingly, the semiconductor device package provides increased device reliability.

    Nonvolatile memory device and an erase method thereof
    4.
    发明授权
    Nonvolatile memory device and an erase method thereof 有权

    公开(公告)号：US10438666B2

    公开(公告)日：2019-10-08

    申请号：US16043964

    申请日：2018-07-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Ji-yoon Park ,  Wan-dong Kim ,  Seung-bum Kim ,  Deok-woo Lee ,  You-se Kim ,  Se-hwan Park ,  Jin-woo Park

    IPC: G11C16/16 ,  G11C11/56 ,  G11C16/04 ,  G11C16/34

    Abstract: A method of erasing a memory device, the method of erasing the memory device including: performing, in a first erase period, a first erase operation on memory cells respectively connected to a plurality of word lines, wherein at least one of the memory cells, which is included in a memory block, is not erase-passed; determining, after the first erase period, an erase operation speed by applying a verify voltage to at least one of the plurality of word lines, and determining an effective erasing time for each word line based on the determined erase operation speed; and performing, in a second erase period, a second erase operation on the memory cells respectively connected to the plurality of word lines based on the determined effective erasing times.

    Semiconductor package
    6.
    发明授权
    Semiconductor package 有权

    公开(公告)号：US11329024B2

    公开(公告)日：2022-05-10

    申请号：US16942084

    申请日：2020-07-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Ji-seok Hong ,  Jin-woo Park

    IPC: H01L25/065 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00

    Abstract: A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may be provided.

Patent Agency Ranking