公开(公告)号：US20200243661A1

公开(公告)日：2020-07-30

申请号：US16750826

申请日：2020-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangmin LEE ,  Youngchang YOON ,  Daehoon KWON ,  Jaehyup KIM

IPC: H01L29/43 ,  H01L29/10

Abstract: The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE).An amplifier is provided. The amplifier includes a first resistor electrically connected to the input terminal, a second resistor electrically connected to the output terminal, a switch including a metal-oxide-semiconductor field-effect transistor (MOSFET) and electrically connected to one end of the second resistor, and a switch control processor configured to electrically connect the gate terminal of the MOSFET constituting the switch and the bulk terminal of the MOSFET constituting the switch to an impedance having an impedance value higher than a preset first threshold.

公开(公告)号：US20250077448A1

公开(公告)日：2025-03-06

申请号：US18515094

申请日：2023-11-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joung Won PARK ,  Jaehyup KIM

IPC: G06F13/16

Abstract: A system and method for memory signal timing calibration. In some embodiments, the system includes: a memory input-output circuit, including: a first circuit for generating a first data signal; a second circuit for generating a second data signal; and a first phase control circuit, the first phase control circuit being configured to perform a phase adjustment of a phase of the second data signal.

公开(公告)号：US20240235610A1

公开(公告)日：2024-07-11

申请号：US18176356

申请日：2023-02-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Joung Won PARK ,  Jaehyup KIM

IPC: H04B3/32

CPC classification number: H04B3/32

Abstract: Systems and methods for crosstalk suppression. According to an embodiment of the present disclosure, there is provided a system, including: a first communications channel; and a first crosstalk reduction circuit, the first communications channel being a wired communications channel, and the first crosstalk reduction circuit being configured to: receive a signal from a second communications channel; and modify a signal in the first communications channel to reduce an effect of crosstalk from the second communications channel.

公开(公告)号：US20200244237A1

公开(公告)日：2020-07-30

申请号：US16750552

申请日：2020-01-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangmin LEE ,  Daehoon KWON ,  Jaehyup KIM

IPC: H03F3/24 ,  H03F3/45 ,  H03F1/42 ,  H04B1/40

Abstract: The apparatus relates to a pre-5th-Generation (5G) or 5G communication system to be provided for supporting higher data rates Beyond 4th-Generation (4G) communication system such as Long-Term Evolution (LTE). The disclosure relates to an apparatus including an electronic circuit for amplifying a signal. The apparatus includes a transceiver including an amplification circuit, and at least one processor coupled to the transceiver. The amplification circuit includes a first path to generate a first current corresponding to a voltage of an input signal, a second path to generate a second current corresponding to a voltage of the input signal, a separation unit to control each of the first current and the second current, a current mirror to generate a third current corresponding to the first current, and a folding unit to generate an output signal on the basis of the second current and the third current.

公开(公告)号：US20200227203A1

公开(公告)日：2020-07-16

申请号：US16739564

申请日：2020-01-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngchang YOON ,  Jaehyup KIM ,  Sangmin LEE

IPC: H01F27/29 ,  H03H7/01 ,  H03H7/06 ,  H03H7/38

Abstract: An apparatus is provided. The apparatus includes an electronic circuit for processing a differential signal. A device including an electronic circuit may include a first inductor and a second inductor that process a differential signal, a first circuit connected to the first inductor in parallel, a second circuit connected to the second inductor in parallel, and lines connecting the first inductor and the first circuit, the lines being disposed to pass through an area defined by the first inductor and the second inductor. The first inductor and the second inductor have symmetrical differential structures.