公开(公告)号：US20240057329A1

公开(公告)日：2024-02-15

申请号：US18338757

申请日：2023-06-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhun KIM ,  Jaeick SON

IPC: H10B41/41 ,  H10B41/27 ,  H10B43/27 ,  H10B43/40 ,  H01L23/522 ,  H01L23/528 ,  G11C16/04 ,  H01L25/065

CPC classification number: H10B41/41 ,  H10B41/27 ,  H10B43/27 ,  H10B43/40 ,  H01L23/5226 ,  H01L23/5283 ,  G11C16/0483 ,  H01L25/0657 ,  H01L2225/06541

Abstract: A semiconductor device, and more particularly, to a memory device having a three-dimensional structure are provided. The memory device various example embodiments includes a cell region and a peripheral circuit region that at least partially overlaps the cell region when viewed in plan view. The peripheral circuit region includes a first sub-peripheral circuit region including a substrate and a circuit element on the substrate, and a second sub-peripheral circuit region that is stacked on the first sub-peripheral circuit region in a vertical direction and that includes a sub-poly structure and a circuit element on the sub-poly structure.

公开(公告)号：US20230387053A1

公开(公告)日：2023-11-30

申请号：US17983469

申请日：2022-11-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changhun KIM ,  Jaeick SON

IPC: H01L23/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L24/06 ,  H01L25/0657 ,  H01L25/18 ,  H01L24/08 ,  H01L2224/06515 ,  H01L2224/08145 ,  H01L2924/1431 ,  H01L2924/14511 ,  H01L2924/19104 ,  H01L2924/19043 ,  H01L2924/19041

Abstract: A non-volatile memory device includes a first chip including a first substrate and a circuit element, and a second chip stacked on the first chip. The second chip includes a second substrate including a first cell region and a second cell region, gate electrodes stacked on the second cell region of the second substrate, wherein the gate electrodes are between the second substrate and the first chip, an upper insulating layer configured to cover the second substrate, dummy pads and input/output pads on the upper insulating layer, a cover layer on the upper insulating layer to cover the dummy pads, wherein the cover layer is configured to expose the input/output pads to an outside, and dummy contact plugs on one side of the second substrate, wherein the dummy contact plugs are configured to penetrate the upper insulating layer and electrically connect the dummy pads and the circuit element.