公开(公告)号：US20220084939A1

公开(公告)日：2022-03-17

申请号：US17223144

申请日：2021-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jaejin LEE ,  Hana KIM ,  Jaewha PARK ,  Dongchan LIM

IPC: H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L21/768

Abstract: A wiring structure includes a filling metal, a cover metal including cobalt (Co) on the filling metal, the cover metal having a first portion along a side surface and along a lower surface of the filling metal, and a second portion along an upper surface of the filling metal, a barrier metal on an outer surface of the first portion of the cover metal, and a capping metal on an outer surface of the second portion of the cover metal, the capping metal including a cobalt (Co) alloy, wherein the filling metal has higher conductivity than the cover metal and the barrier metal.

公开(公告)号：US20220344347A1

公开(公告)日：2022-10-27

申请号：US17520868

申请日：2021-11-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewha PARK ,  Moonkeun KIM ,  Sukhoon KIM ,  Dongchan LIM

IPC: H01L27/108

Abstract: A semiconductor device manufacturing method according to the exemplary embodiments of the disclosure includes patterning a substrate, thereby forming an active pattern, forming a trench penetrating the active pattern, forming a support layer covering the trench, forming a first opening at the support layer, forming a gate electrode layer filling the trench through the first opening, and forming a bit line structure electrically connected to the active pattern. The support layer includes a base portion covering a top surface of the active pattern, and a support disposed in the trench.

公开(公告)号：US20230397393A1

公开(公告)日：2023-12-07

申请号：US18207689

申请日：2023-06-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaewha PARK ,  Moonkeun KIM ,  Sukhoon KIM ,  Dongchan LIM

IPC: H10B12/00

CPC classification number: H10B12/053 ,  H10B12/34 ,  H10B12/315 ,  H10B12/482

Abstract: A semiconductor device manufacturing method according to the exemplary embodiments of the disclosure includes patterning a substrate, thereby forming an active pattern, forming a trench penetrating the active pattern, forming a support layer covering the trench, forming a first opening at the support layer, forming a gate electrode layer filling the trench through the first opening, and forming a bit line structure electrically connected to the active pattern. The support layer includes a base portion covering a top surface of the active pattern, and a support disposed in the trench.