公开(公告)号：US20150228573A1

公开(公告)日：2015-08-13

申请号：US14457185

申请日：2014-08-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je-Min PARK ,  Yoo-Sang HWANG

IPC: H01L23/528 ,  H01L23/522 ,  H01L23/538 ,  H01L23/535

CPC classification number: H01L23/5386 ,  H01L23/535 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10894 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided is a semiconductor device. The semiconductor device includes a semiconductor substrate having a contact region. An interlayer insulating layer is disposed on the semiconductor substrate. A lower contact plug passing through the interlayer insulating layer and electrically connected to the contact region is disposed. An interconnection structure is disposed on the interlayer insulating layer. An adjacent interconnection spaced apart from the interconnection structure is disposed on the interlayer insulating layer. A bottom surface of the interconnection structure includes a first part overlapping a part of an upper surface of the lower contact plug, and a second part overlapping the interlayer insulating layer.

Abstract translation: 提供一种半导体器件。 半导体器件包括具有接触区域的半导体衬底。 层间绝缘层设置在半导体衬底上。 设置穿过层间绝缘层并电连接到接触区域的下接触插塞。 互连结构设置在层间绝缘层上。 与互连结构间隔开的相邻互连设置在层间绝缘层上。 互连结构的底表面包括与下接触插塞的上表面的一部分重叠的第一部分和与层间绝缘层重叠的第二部分。

公开(公告)号：US20150111360A1

公开(公告)日：2015-04-23

申请号：US14515874

申请日：2014-10-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Wan KIM ,  Byeung-Chul KIM ,  Bong-Soo KIM ,  Je-Min PARK ,  Yoo-Sang HWANG

IPC: H01L27/108 ,  H01L21/3213 ,  H01L29/423 ,  H01L21/3205 ,  H01L49/02 ,  H01L21/768

CPC classification number: H01L27/10855 ,  H01L21/32139 ,  H01L21/7685 ,  H01L21/76877 ,  H01L27/10814 ,  H01L27/10823 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L27/10894 ,  H01L27/10897 ,  H01L28/91 ,  H01L29/4236

Abstract: A method of manufacturing a semiconductor device includes forming a first conductive layer on a substrate, partially removing the first conductive layer and an upper portion of the substrate to form a recess, forming a second conductive layer pattern to fill the recess, forming a third conductive layer on the second conductive layer pattern and the first conductive layer, and patterning the third conductive layer and the second conductive layer pattern to form a bit line structure and a bit line contact, respectively.

Abstract translation: 制造半导体器件的方法包括在衬底上形成第一导电层，部分地去除第一导电层和衬底的上部以形成凹陷，形成第二导电层图案以填充凹部，形成第三导电 在第二导电层图案和第一导电层上的层，并且分别构图第三导电层和第二导电层图案以形成位线结构和位线接触。

公开(公告)号：US20140327063A1

公开(公告)日：2014-11-06

申请号：US14255365

申请日：2014-04-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je-Min PARK

IPC: H01L27/108

CPC classification number: H01L27/10855 ,  H01L21/76897 ,  H01L27/10814 ,  H01L27/10888

Abstract: A semiconductor device including a substrate, the substrate including active regions; a pair of conductive lines spaced apart from the substrate such that an insulating layer is between the substrate and the pair of conductive lines; insulating spacers covering side walls of each of the pair of conductive lines such that contact holes having first widths in a first direction are defined between the pair of conductive lines; upper insulating patterns on the pair of conductive lines, the upper insulating patterns defining landing pad holes connected to the contact holes such that the landing pad holes have second widths in the first direction that are greater than the first widths; contact structures including contact plugs connected to the active regions by passing through the insulating layer, and first landing pads connected to the contact plugs, the first landing pads being in the landing pads holes such that the first landing pads vertically overlap with one of the pair of conductive lines; and capacitor lower electrodes connected to the contact structures.

Abstract translation: 一种包括衬底的半导体器件，所述衬底包括有源区; 一对与衬底间隔开的导电线，使得绝缘层位于衬底和一对导电线之间; 绝缘间隔物，覆盖所述一对导线中的每一个的侧壁，使得在所述一对导线之间限定具有第一方向的第一宽度的接触孔; 所述一对导线上的上绝缘图案，所述上绝缘图案限定着接地焊盘孔连接到所述接触孔，使得所述着陆焊盘孔具有在所述第一方向上具有大于所述第一宽度的第二宽度; 接触结构，包括通过穿过绝缘层连接到有源区的接触插塞，以及连接到接触插塞的第一着陆焊盘，第一着陆焊盘位于着陆焊盘孔中，使得第一着陆焊盘与该对中的一个垂直重叠 的导线; 和连接到接触结构的电容器下电极。

公开(公告)号：US20210091086A1

公开(公告)日：2021-03-25

申请号：US17112195

申请日：2020-12-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Augustin Jinwoo HONG ,  Young-Ju LEE ,  Joon-Yong CHOE ,  Jung-hyun KIM ,  Sang-jun LEE ,  Hyeon-Kyu LEE ,  Yoon-Chul CHO ,  Je-Min PARK ,  Hyo-Dong BAN

IPC: H01L27/108 ,  H01L21/768 ,  H01L23/535

Abstract: A memory device includes cell transistors on active regions defined by a device isolation layer on a substrate such that each cell transistor has a buried cell gate and a junction portion adjacent to and at least partially distal to the substrate in relation to the buried cell gate, an insulation pattern on the substrate and covering the cell transistors and the device isolation layer, and a bit line structure on the insulation pattern and connected to the junction portion. The bit line structure includes a buffer pattern on the pattern and having a thermal oxide pattern, a conductive line on the buffer pattern, and a contact extending from the conductive line to the junction portion through the buffer pattern and the insulation pattern.

公开(公告)号：US20140312455A1

公开(公告)日：2014-10-23

申请号：US14175257

申请日：2014-02-07

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-Min PARK

IPC: H01L27/108

CPC classification number: H01L21/76229 ,  H01L21/76 ,  H01L27/10876 ,  H01L27/10894

Abstract: A semiconductor device including a plurality of active patterns, a plurality of first isolation layer patterns and a plurality of second isolation layer patterns may be provided. In particular, the active patterns may be arranged both in a first direction and in a second direction, and may protrude from a substrate and have a length in the first direction. The first isolation layer patterns may fill a first space, the first space provided between the active patterns and arranged in the first direction, and support two opposing sidewalls of neighboring active patterns. The second isolation layer patterns may fill a second space between the active patterns and the first isolation layer patterns. Accordingly, the active patterns of the semiconductor device may not collapse or incline because the first isolation layer patterns support the active patterns.

Abstract translation: 可以提供包括多个有源图案，多个第一隔离层图案和多个第二隔离层图案的半导体器件。 特别地，有源图案可以在第一方向和第二方向上布置，并且可以从基板突出并且在第一方向上具有长度。 第一隔离层图案可以填充第一空间，第一空间设置在活动图案之间并且布置在第一方向上，并且支撑相邻活动图案的两个相对的侧壁。 第二隔离层图案可以填充活性图案和第一隔离层图案之间的第二空间。 因此，半导体器件的有源图案可能不会折叠或倾斜，因为第一隔离层图案支持活动图案。

公开(公告)号：US20140145268A1

公开(公告)日：2014-05-29

申请号：US14017502

申请日：2013-09-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Je-Min PARK ,  Dae-Ik KIM

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L27/10894 ,  H01L21/76831 ,  H01L23/485 ,  H01L23/5222 ,  H01L27/10888 ,  H01L29/4236 ,  H01L29/78 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes an insulating interlayer over a substrate in a first region, the insulating layer including contact holes exposing a portion of a surface of the substrate, and contact plugs in the contact holes. The contact plugs include a stacked structure of a first barrier metal layer pattern and a first metal layer pattern. The semiconductor device also includes second metal layer patterns directly contacting with the contact plugs and an upper surface of the insulating interlayer. The second metal layer pattern consists is a metal material layer.

Abstract translation: 半导体器件包括在第一区域中的衬底上的绝缘中间层，所述绝缘层包括暴露衬底表面的一部分的接触孔以及接触孔中的接触插塞。 接触插塞包括第一阻挡金属层图案和第一金属层图案的堆叠结构。 半导体器件还包括与接触插塞直接接触的第二金属层图案和绝缘中间层的上表面。 第二金属层图案是金属材料层。