公开(公告)号：US20240355741A1

公开(公告)日：2024-10-24

申请号：US18760444

申请日：2024-07-01

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shuen-Shin LIANG ,  Chun-I TSAI ,  Chih-Wei CHANG ,  Chun-Hsien HUANG ,  Hung-Yi HUANG ,  Keng-Chu LIN ,  Ken-Yu CHANG ,  Sung-Li WANG ,  Chia-Hung CHU ,  Hsu-Kai CHANG

IPC分类号： H01L23/532 ,  H01L21/285 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/53266 ,  H01L21/76802 ,  H01L21/7685 ,  H01L21/28568 ,  H01L21/76843 ,  H01L23/5226

摘要： The present disclosure describes a method for forming capping layers configured to prevent the migration of out-diffused cobalt atoms into upper metallization layers In some embodiments, the method includes depositing a cobalt diffusion barrier layer on a liner-free conductive structure that includes ruthenium, where depositing the cobalt diffusion barrier layer includes forming the cobalt diffusion barrier layer self-aligned to the liner-free conductive structure. The method also includes depositing, on the cobalt diffusion barrier layer, a stack with an etch stop layer and dielectric layer, and forming an opening in the stack to expose the cobalt diffusion barrier layer. Finally, the method includes forming a conductive structure on the cobalt diffusion barrier layer.

公开(公告)号：US20240170328A1

公开(公告)日：2024-05-23

申请号：US18514461

申请日：2023-11-20

申请人： IMEC VZW

发明人： Anshul Gupta ,  Zsolt Tokei ,  Stefan Decoster

IPC分类号： H01L21/768

CPC分类号： H01L21/76802 ,  H01L21/7684 ,  H01L21/7685 ,  H01L21/76877

摘要： A method includes forming and patterning a first dielectric over a substrate; covering the first dielectric with metal and planarizing the metal exposing a surface of the first dielectric and forming a first metal; forming a second dielectric over the first dielectric and the first metal; covering the second dielectric with metal and planarizing the metal exposing a surface of the second dielectric and forming a second metal; forming a mask over the second dielectric and the second metal; and transferring: a first sub-pattern of the mask into a first portion of the first metal to form a lower metal, a second sub-pattern of the mask into a first portion of the second metal and a second portion of the first metal to form a stacked metal, and a third sub-pattern of the mask into a second portion of the second metal to form an upper metal.

公开(公告)号：US20240113026A1

公开(公告)日：2024-04-04

申请号：US18526127

申请日：2023-12-01

申请人： Infineon Technologies AG

发明人： Edward Fürgut ,  Ravi Keshav Joshi ,  Thomas Basler ,  Martin Gruber ,  Jochen Hilsenbeck ,  Wolfgang Scholz

IPC分类号： H01L23/532 ,  H01L21/768 ,  H01L23/00 ,  H01L29/16 ,  H01L29/45

CPC分类号： H01L23/53238 ,  H01L21/7685 ,  H01L24/45 ,  H01L29/1608 ,  H01L29/45 ,  H01L2224/05172 ,  H01L2224/05179 ,  H01L2224/05181 ,  H01L2224/05672 ,  H01L2224/05679 ,  H01L2224/45139 ,  H01L2224/45144 ,  H01L2224/45147

摘要： A silicon carbide device includes a silicon carbide substrate, a contact layer located on the silicon carbide substrate and including nickel and silicon, a barrier layer structure including titanium and tungsten, and a metallization layer comprising copper, wherein the contact layer is located between the silicon carbide substrate and at least a part of the barrier layer structure, wherein the barrier layer structure is located between the silicon carbide substrate and the metallization layer, wherein the metallization layer is configured as a contact pad of the silicon carbide device.

公开(公告)号：US11935934B2

公开(公告)日：2024-03-19

申请号：US17502737

申请日：2021-10-15

申请人： SK hynix Inc.

发明人： Young Gwang Yoon

IPC分类号： H01L29/423 ,  H01L21/02 ,  H01L21/768 ,  H01L29/40 ,  H01L29/51

CPC分类号： H01L29/4236 ,  H01L21/022 ,  H01L21/76849 ,  H01L21/7685 ,  H01L29/401 ,  H01L29/513

摘要： The present invention provides a semiconductor device including a capping layer of a reduced thickness and capable of preventing regrowth of an interface layer caused by oxygen injection, and a method for fabricating the same. According to an embodiment of the present invention, the semiconductor device comprises: an interface layer on a substrate; a high-k layer on the interface layer; a gate electrode on the high-k layer; and a capping layer including a first oxygen barrier layer and a second oxygen barrier layer on the gate electrode.

公开(公告)号：US11923291B2

公开(公告)日：2024-03-05

申请号：US17007626

申请日：2020-08-31

申请人： Kioxia Corporation

发明人： Atsushi Kato

IPC分类号： H01L23/522 ,  H01L21/768 ,  H01L23/00

CPC分类号： H01L23/5226 ,  H01L21/76849 ,  H01L21/7685 ,  H01L21/76856 ,  H01L21/76864 ,  H01L24/08 ,  H01L21/7684 ,  H01L2224/08112 ,  H01L2224/08145

摘要： A semiconductor device includes a first substrate, a logical circuit, a first insulating film, a wiring, a plug, and a first layer containing a metal oxide or a metal nitride. The logical circuit is disposed on the first substrate. The first insulating film is disposed above the logical circuit. The wiring includes a first film disposed in the first insulating film, the first film extending in a first direction along an upper surface of the first substrate, and the first film containing a metal, and a first metal layer disposed in the first insulating film via the first film. The plug is disposed under the wiring, extends in a second direction that intersects the first direction, and is electrically connected to the wiring. The first layer is provided between an upper end of the plug and a bottom end of the wiring.

公开(公告)号：US20230402321A1

公开(公告)日：2023-12-14

申请号：US18447539

申请日：2023-08-10

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Po-Hsien CHENG ,  Chi-Ming YANG ,  Tze-Liang LEE

IPC分类号： H01L21/768 ,  H01L23/532

CPC分类号： H01L21/76846 ,  H01L23/53238 ,  H01L23/53209 ,  H01L21/76844 ,  H01L21/7685 ,  H01L23/53266 ,  H01L23/5226

摘要： A layer of carbon (e.g., graphite or graphene) at a metal interface (e.g., between an MEOL interconnect and a gate contact or a source or drain region contact, between an MEOL contact plug and a BEOL metallization layer, and/or between BEOL conductive structures) is used to reduce contact resistance at the metal interface, which increases electrical performance of an electronic device. Additionally, in some implementations, the layer of carbon may help prevent heat transfer from a second metal to a first metal when the second metal is deposited over the first metal. This results in more symmetric deposition of the second metal, which reduces surface roughness and contact resistance at the metal interface. As an alternative, in some implementations, the layer of carbon is etched before deposition of the second metal in order to reduce contact resistance at the metal interface.

公开(公告)号：US11798846B2

公开(公告)日：2023-10-24

申请号：US17142750

申请日：2021-01-06

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chih-Hsuan Lin ,  Xi-Zong Chen ,  Chih-Teng Liao

IPC分类号： H01L21/768 ,  H01L21/285

CPC分类号： H01L21/76897 ,  H01L21/28518 ,  H01L21/7685 ,  H01L21/76829 ,  H01L21/76846

摘要： The present disclosure provides embodiments of a semiconductor device. In one embodiment, the semiconductor device includes a gate structure, a source/drain feature adjacent the gate structure, a first dielectric layer over the source/drain feature, an etch stop layer over the gate structure and the first dielectric layer, a second dielectric layer over the etch stop layer, a source/drain contact that includes a first portion extending through the first dielectric layer and a second portion extending through the etch stop layer and the second dielectric layer, a metal silicide layer disposed between the second portion and etch stop layer, and a metal nitride layer disposed between the first portion and the first dielectric layer.

公开(公告)号：US20230253312A1

公开(公告)日：2023-08-10

申请号：US18301447

申请日：2023-04-17

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chieh-Han Wu ,  Cheng-Hsiung Tsai ,  Chih Wei Lu ,  Chung-Ju Lee

IPC分类号： H01L23/522 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L23/5226 ,  H01L21/7685 ,  H01L21/76802 ,  H01L21/76816 ,  H01L21/76829 ,  H01L21/76843 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266

摘要： Interconnect structures and methods of forming the same are provided. An interconnect structure according to the present disclosure includes a conductive line feature over a substrate, a conductive etch stop layer over the conductive line feature, a contact via over the conductive etch stop layer, and a barrier layer disposed along a sidewall of the conductive line feature, a sidewall of the conductive etch stop layer, and a sidewall of the contact via.

公开(公告)号：US11652044B2

公开(公告)日：2023-05-16

申请号：US17187143

申请日：2021-02-26

申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.

发明人： Shu-Cheng Chin ,  Yao-Min Liu ,  Hung-Wen Su ,  Chih-Chien Chi ,  Chi-Feng Lin

IPC分类号： H01L23/522 ,  H01L23/528 ,  H01L29/417 ,  H01L29/45 ,  H01L21/768 ,  H01L23/532

CPC分类号： H01L23/5226 ,  H01L21/7685 ,  H01L21/76846 ,  H01L21/76883 ,  H01L23/5283 ,  H01L29/41725 ,  H01L29/456 ,  H01L21/76807 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266

摘要： A semiconductor device includes an insulating layer, wherein the insulating layer has a via opening and a conductive line opening. The semiconductor device further includes a via in the via opening, wherein the via includes a first conductive material. The semiconductor device further includes a conductive line in the conductive line opening. The conductive line includes a first liner layer, wherein a first thickness of the first liner layer over the via is less than a second thickness of the first liner layer over the insulating layer, and a conductive fill comprising a second conductive material different from the first conductive material.

公开(公告)号：US20230141895A1

公开(公告)日：2023-05-11

申请号：US17520991

申请日：2021-11-08

申请人： NANYA TECHNOLOGY CORPORATION

发明人： CHUN-CHENG LIAO

IPC分类号： H01L21/768 ,  H01L23/522

CPC分类号： H01L21/76897 ,  H01L21/7685 ,  H01L21/76885 ,  H01L23/5226 ,  H01L21/76864

摘要： A method for preparing a semiconductor device structure includes forming a first dielectric layer over a semiconductor substrate; forming a first conductive plug in the first dielectric layer; forming a polysilicon layer covering the first dielectric layer and the first conductive plug; transforming a portion of the polysilicon layer into a silicide portion; forming a second conductive plug directly over the silicide portion; and forming a second dielectric layer surrounding the second conductive plug.