公开(公告)号：US20220130798A1

公开(公告)日：2022-04-28

申请号：US17569657

申请日：2022-01-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-seok HONG ,  Jin-woo PARK

IPC: H01L25/065 ,  H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L25/00

Abstract: A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may be provided.

公开(公告)号：US20200075544A1

公开(公告)日：2020-03-05

申请号：US16366044

申请日：2019-03-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ji-seok HONG ,  Jin-woo PARK

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00 ,  H01L23/48 ,  H01L21/768

Abstract: A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may be provided.