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公开(公告)号：US20160079163A1
公开(公告)日：2016-03-17
申请号：US14727785
申请日：2015-06-01
发明人： Jin-woo PARK
IPC分类号： H01L23/522 , H01L23/498 , H01L23/31
CPC分类号： H01L23/49811 , H01L21/76898 , H01L23/3128 , H01L23/3192 , H01L23/481 , H01L24/03 , H01L24/05 , H01L24/16 , H01L2224/02126 , H01L2224/02313 , H01L2224/0345 , H01L2224/03452 , H01L2224/03462 , H01L2224/0347 , H01L2224/0401 , H01L2224/05009 , H01L2224/05552 , H01L2224/05554 , H01L2224/05556 , H01L2224/05557 , H01L2224/05558 , H01L2224/05562 , H01L2224/0557 , H01L2224/05571 , H01L2224/05572 , H01L2224/06051 , H01L2224/131 , H01L2224/16145 , H01L2224/16146 , H01L2224/16225 , H01L2224/16237 , H01L2924/15174 , H01L2924/15311 , H01L2924/181 , H01L2924/00012 , H01L2924/00014 , H01L2924/014
摘要： A semiconductor package comprising: a semiconductor chip comprising a first surface on a first side of the semiconductor chip and a second surface on a second side of the semiconductor chip, wherein the first side and the second side are opposite sides of the semiconductor chip; a through-electrode penetrating the semiconductor chip between the first surface and the second surface; a passivation layer formed on the second surface of the semiconductor chip; and an electrode pad formed on an upper surface of the passivation layer and electrically connected to the through-electrode, wherein the passivation layer comprises a first passivation layer formed on the second surface of the semiconductor chip and a second passivation layer formed on an upper surface of the first passivation layer, and the electrode pad penetrates the second passivation layer to contact the upper surface of the first passivation layer.
摘要翻译： 一种半导体封装，包括：半导体芯片，其包括在所述半导体芯片的第一侧上的第一表面和所述半导体芯片的第二侧上的第二表面，其中所述第一侧和所述第二侧是所述半导体芯片的相对侧; 在所述第一表面和所述第二表面之间穿透所述半导体芯片的穿透电极; 形成在所述半导体芯片的第二表面上的钝化层; 以及形成在所述钝化层的上表面上并电连接到所述通孔的电极焊盘，其中所述钝化层包括形成在所述半导体芯片的第二表面上的第一钝化层和形成在所述上表面上的第二钝化层 并且电极焊盘穿透第二钝化层以接触第一钝化层的上表面。
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公开(公告)号：US20220130798A1
公开(公告)日：2022-04-28
申请号：US17569657
申请日：2022-01-06
发明人： Ji-seok HONG , Jin-woo PARK
IPC分类号： H01L25/065 , H01L21/768 , H01L23/48 , H01L23/00 , H01L25/00
摘要： A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may be provided.
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公开(公告)号：US20210384143A1
公开(公告)日：2021-12-09
申请号：US17168337
申请日：2021-02-05
发明人： Jin-woo PARK , Un-Byoung KANG , Jong Ho LEE
IPC分类号： H01L23/00 , H01L23/14 , H01L23/498
摘要： A semiconductor package includes a first substrate including a circuit pattern and a dummy pattern on an upper face of the first substrate, a solder ball, a second substrate on the first substrate, and an underfill material layer between the first and second substrates. The underfill material layer wraps around the solder ball. The dummy pattern is not electrically connected to the circuit pattern. The first substrate includes a solder resist layer on the circuit pattern and the dummy pattern. The solder resist layer includes a first opening for exposing at least a part of the circuit pattern. The solder ball is in the first opening and electrically insulated from the dummy pattern by the solder resist layer. The second substrate is electrically connected to the first substrate by the solder ball. The second substrate is electrically insulated from the dummy pattern by the solder resist layer.
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公开(公告)号：US20190096869A1
公开(公告)日：2019-03-28
申请号：US16201021
申请日：2018-11-27
发明人： Young Lyong KIM , Jin-woo PARK , CHOONGBIN YIM , Younji MIN
IPC分类号： H01L25/00 , H01L25/10 , H01L23/538 , H01L23/31 , H01L23/29 , H01L23/00 , H01L21/56 , H01L25/065
摘要： Provided are a semiconductor package and a method of manufacturing the same. The semiconductor package comprises a substrate, a semiconductor chip on the substrate, an interconnect substrate spaced apart from the semiconductor chip on the substrate and including a conductive member therein, a solder ball on the interconnect substrate and electrically connected to the conductive member, a polymer layer on the interconnect substrate and the semiconductor chip and including an opening through which the solder ball is exposed, and polymer particles in the solder ball and including the same material as the polymer layer.
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公开(公告)号：US20200075544A1
公开(公告)日：2020-03-05
申请号：US16366044
申请日：2019-03-27
发明人： Ji-seok HONG , Jin-woo PARK
IPC分类号： H01L25/065 , H01L25/00 , H01L23/00 , H01L23/48 , H01L21/768
摘要： A semiconductor package including a first device layer including first semiconductor devices, a first cover insulating layer, and first through-electrodes passing through at least a portion of the first device layer, a second device layer second semiconductor devices, a second cover insulating layer, and second through-electrodes passing through at least a portion of the second device layer, the second semiconductor devices vertically overlapping the first semiconductor devices, respectively, the second cover insulating layer in contact with the first cover insulating layer a third device layer including an upper semiconductor chip, the upper semiconductor chip vertically overlapping both at least two of first semiconductor devices and at least two of the second semiconductor devices, and device bonded pads passing through the first and second cover insulating layers, the device bonded pads electrically connecting the first and second through-electrodes to the upper semiconductor chip may be provided.
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公开(公告)号：US20140103523A1
公开(公告)日：2014-04-17
申请号：US14045881
申请日：2013-10-04
发明人： Jae-gwon JANG , Young-lyong KIM , Jin-woo PARK , Ae-nee JANG
IPC分类号： H01L23/498
CPC分类号： H01L23/49838 , H01L23/49811 , H01L25/0652 , H01L25/0657 , H01L2224/16145 , H01L2224/32145 , H01L2224/48227 , H01L2224/73207 , H01L2224/81193 , H01L2225/0651 , H01L2225/06513 , H01L2924/15311
摘要： A semiconductor package including a lower semiconductor chip, and an upper semiconductor chip flip-chip bonded on the lower semiconductor chip may be provided. Each of the lower and upper semiconductor chips includes a first bonding pad formed on an active surface, which has a center line extending in a first direction, and a first rewire electrically connected to the first bonding pad, The first rewire includes first and second connection regions. The first and second connection regions face each other and are disposed at a same distance from the center line in a second direction, which is perpendicular to the first direction.
摘要翻译： 可以提供包括下半导体芯片的半导体封装和结合在下半导体芯片上的上半导体芯片倒装芯片。 下半导体芯片和上半导体芯片中的每一个包括形成在有源表面上的第一焊盘，该焊盘具有沿第一方向延伸的中心线，以及电连接到第一焊盘的第一重新布线。第一布线包括第一和第二连接 地区。 第一连接区域和第二连接区域彼此面对，并且在与第一方向垂直的第二方向上以与中心线相同的距离设置。
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公开(公告)号：US20240162194A1
公开(公告)日：2024-05-16
申请号：US18421198
申请日：2024-01-24
发明人： Jaekyung YOO , Jayeon LEE , Jae-eun LEE , Yeongkwon KO , Jin-woo PARK , Teak Hoon LEE
IPC分类号： H01L25/065 , H01L23/13 , H01L23/31 , H01L23/498 , H01L25/00
CPC分类号： H01L25/0657 , H01L23/13 , H01L23/3157 , H01L23/49822 , H01L23/49838 , H01L25/50 , H01L2225/06513 , H01L2225/06541 , H01L2225/06586
摘要： Disclosed are semiconductor packages and/or methods of fabricating the same. The semiconductor package comprises a package substrate, a first semiconductor chip mounted on the package substrate, a second semiconductor chip mounted on a top surface of the first semiconductor chip, and a first under-fill layer that fills a space between the package substrate and the first semiconductor chip. The package substrate includes a cavity in the package substrate, and a first vent hole that extends from a top surface of the package substrate and is in fluid communication with the cavity. The first under-fill layer extends along the first vent hole to fill the cavity.
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公开(公告)号：US20230253343A1
公开(公告)日：2023-08-10
申请号：US18301606
申请日：2023-04-17
发明人： Jin-woo PARK , Un-Byoung KANG , Jong Ho LEE
IPC分类号： H01L23/00 , H01L23/498 , H01L23/14
CPC分类号： H01L23/562 , H01L23/49816 , H01L24/14 , H01L23/14
摘要： A semiconductor package includes a first substrate including a circuit pattern and a dummy pattern on an upper face of the first substrate, a solder ball, a second substrate on the first substrate, and an underfill material layer between the first and second substrates. The underfill material layer wraps around the solder ball. The dummy pattern is not electrically connected to the circuit pattern. The first substrate includes a solder resist layer on the circuit pattern and the dummy pattern. The solder resist layer includes a first opening for exposing at least a part of the circuit pattern. The solder ball is in the first opening and electrically insulated from the dummy pattern by the solder resist layer. The second substrate is electrically connected to the first substrate by the solder ball. The second substrate is electrically insulated from the dummy pattern by the solder resist layer.
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公开(公告)号：US20230243705A1
公开(公告)日：2023-08-03
申请号：US17979925
申请日：2022-11-03
发明人： Jin-woo PARK , Seung-Rok KIM , Soyeon LEE , Ey-In LEE
摘要： A temperature sensor includes a first electrode, second electrode, and a pyroelectric layer between the first electrode and the second electrode. The pyroelectric layer includes a ferroelectric polymer and an ionogel.
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公开(公告)号：US20230111343A1
公开(公告)日：2023-04-13
申请号：US17961954
申请日：2022-10-07
发明人： Choong Bin YIM , Ji Hwang KIM , Jin-woo PARK , Jong Bo SHIM
IPC分类号： H01L25/10 , H01L25/00 , H01L23/00 , H01L21/56 , H01L23/538
摘要： A semiconductor package includes a first wiring structure which includes a first insulating layer, and a first wiring pad inside the first insulating layer, a first semiconductor chip on the first wiring structure, a second wiring structure on the first semiconductor chip, and a connecting member between the first wiring structure and the second wiring structure. The second wiring structure includes a second insulating layer and a plurality of second wiring pads in the second insulating layer which each directly contact one surface of the first semiconductor chip.
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