Encryption circuit for performing virtual encryption operations

    公开(公告)号:US11328097B2

    公开(公告)日:2022-05-10

    申请号:US16521937

    申请日:2019-07-25

    Abstract: An encryption circuit includes a pipelined encryption core having a plurality of round cores therein. The pipelined encryption core is configured to perform a real round operation on each of a plurality of pieces of input data received therein and generate encryption data from the input data using an encryption operation comprising the real round operation. An encryption controller is provided, which is coupled to the pipelined encryption core. The encryption controller is configured to control the pipelined encryption core so that at least one of the plurality of round cores performs a virtual round operation as part of the encryption operation. The pipelined encryption core is configured to perform a virtual encryption operation using at least one of: (i) dummy data, and (ii) a dummy encryption key.

    MODULAR ARITHMATIC UNIT AND SECURE SYSTEM INCLUDING THE SAME
    4.
    发明申请
    MODULAR ARITHMATIC UNIT AND SECURE SYSTEM INCLUDING THE SAME 有权
    模块化算法和安全系统,包括它们

    公开(公告)号:US20130311531A1

    公开(公告)日:2013-11-21

    申请号:US13734520

    申请日:2013-01-04

    CPC classification number: G06F7/72 G06F7/728

    Abstract: A modular arithmetic unit includes a first input generator receiving first data to generate a first operand; a second input generator receiving second data to generate a second operand; an accumulator performing an accumulate/shift operation to add the first and second operands and outputting the carry and sum; a carry propagation adder adding the carry and the sum to output a result; and a data handler receiving either external data or the result and outputting the first data and the second data.

    Abstract translation: 模块运算单元包括接收第一数据以产生第一操作数的第一输入发生器; 接收第二数据以产生第二操作数的第二输入发生器; 累加器执行累加/移位操作以添加第一和第二操作数并输出进位和和; 一个进位传播加法器,加上进位和和输出一个结果; 以及接收外部数据或结果并输出第一数据和第二数据的数据处理器。

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