-
公开(公告)号：US20240021261A1
公开(公告)日：2024-01-18
申请号：US18475968
申请日：2023-09-27
发明人： Eunhye Oh , Jaehyeok Kim , Yong Ki Lee , Gapkyoung Kim , Taewook Park
CPC分类号： G11C29/42 , G11C29/4401 , G11C29/10 , G11C29/36
摘要： A memory device includes a memory module and a BIST logic circuit. The BIST logic circuit includes; a pattern generator configured to generate first main data including a first portion, an error correction code (ECC) encoder configured to generate first parity data based on the first main data, and a parity control circuit configured to generate mask data based on the first parity data and the first main data, and generate first substituted parity data based on the mask data and the first parity data, wherein a pattern of the first substituted parity data is the same as a pattern of the first portion of the first main data.
-
公开(公告)号：US09098381B2
公开(公告)日：2015-08-04
申请号：US13734520
申请日：2013-01-04
发明人： Kyoungmoon Ahn , Jonghoon Shin , Yong Ki Lee , Ji-Su Kang , Sun-Soo Shin
IPC分类号： G06F7/72
摘要： A modular arithmetic unit includes a first input generator receiving first data to generate a first operand; a second input generator receiving second data to generate a second operand; an accumulator performing an accumulate/shift operation to add the first and second operands and outputting the carry and sum; a carry propagation adder adding the carry and the sum to output a result; and a data handler receiving either external data or the result and outputting the first data and the second data.
摘要翻译： 模块运算单元包括接收第一数据以产生第一操作数的第一输入发生器; 接收第二数据以产生第二操作数的第二输入发生器; 累加器执行累加/移位操作以添加第一和第二操作数并输出进位和和; 一个进位传播加法器，加上进位和和输出一个结果; 以及接收外部数据或结果并输出第一数据和第二数据的数据处理器。
-
公开(公告)号：US09841950B2
公开(公告)日：2017-12-12
申请号：US15242768
申请日：2016-08-22
发明人： Yong Ki Lee , Jonghoon Shin , KyoungMoon Ahn , Ji-Su Kang , Sun-Soo Shin
IPC分类号： G06F7/72
摘要： A modular multiplier and a modular multiplication method are provided. The modular multiplier includes: a first register which stores a previous accumulation value calculated at a previous cycle; a second register which stores a previous quotient calculated at the previous cycle; a quotient generator which generates a quotient using the stored previous accumulation value output from the first register; and an accumulator which receives an operand, a bit value of a multiplier, the stored previous accumulation value, and the stored previous quotient to calculate an accumulation value in a current cycle, wherein the calculated accumulation value is updated to the first register, and the generated quotient is updated to the second register.
-
公开(公告)号：US09811318B2
公开(公告)日：2017-11-07
申请号：US14672656
申请日：2015-03-30
发明人： Jonghoon Shin , Sun-Soo Shin , Kyoungmoon Ahn , Yong Ki Lee
CPC分类号： G06F7/728 , G06F7/5338
摘要： A Montgomery multiplier includes a partial product computing unit for multiplying a multiplicand and a multiplier; a modulus reduction computing unit for performing a multiplication of a modulus and a quotient that reflects a quotient sign; an accumulation unit for accumulating in a intermediate value an output value of the partial product computing unit and an output value of the modulus reduction computing unit from a previous cycle; a quotient computing unit for receiving an accumulation value of the accumulation unit during a current cycle and calculating a quotient sign to be used during a next cycle; and a quotient sign determination unit for determining a quotient sign to be used during a next cycle from the multiplicand, the multiplier and the quotient.
-
公开(公告)号：US09798897B2
公开(公告)日：2017-10-24
申请号：US14577608
申请日：2014-12-19
发明人： Yong Ki Lee , Yun-Ho Youm , Hong-Mook Choi , Jinsu Hyun , KeeMoon Chun
CPC分类号： G06F21/72 , G06F21/556 , G09C1/00 , H04L9/003 , H04L2209/34
摘要： A method of encoding and an encoder are provided. The method includes generating first one-hot bits for most significant bits (MSBs) and second one-hot bits for least significant bits (LSBs) using input one-hot bits; encoding the first one-hot bits to the MSBs and complementary MSBs through a first logical operation using a cross-connection; and encoding the second one-hot bits to the LSBs and complementary LSBs through a second logical operation using a cross-connection. The encoder includes a first bit generator, a first encoder, a second bit generator and a second encoder.
-
公开(公告)号：US10476681B2
公开(公告)日：2019-11-12
申请号：US16140019
申请日：2018-09-24
发明人： Yongsoo Kim , Mijung Noh , Bohdan Karpinskyy , Kyoungmoon Ahn , Yong Ki Lee , Yunhyeok Choi
摘要： A semiconductor device includes a physical unclonable function (PUF) cell array that includes PUF cells outputting first bits; a non-volatile memory that stores marking bits indicating whether the first bits are valid, first mask bits generated by masking second bits depending on parity of the second bits, and second mask bits generated by masking helper bits of the second bits, the second bits are valid bits from the first bits; an extracting unit that extracts the second bits from the first bits using the marking bits; an unmasking unit that unmasks the second bits using the first mask bits while receiving the second bits to provide the third bits; a bit decoding unit that compresses the third bits to fourth bits while receiving the third bits; and a block decoding unit that generates a security key by decoding the fourth bits and the second mask bits.
-
公开(公告)号：US10177913B2
公开(公告)日：2019-01-08
申请号：US14713120
申请日：2015-05-15
发明人： Heon Soo Lee , Yong Ki Lee , Sang Hyun Park , Mi Jung Noh , Hong Mook Choi , Dong Jin Park , Woo Hyung Chun
摘要： A semiconductor device may include: a bus; first and second function modules configured to communicate via the bus; a first encryption module configured to encrypt first data output from the first function module using a first encryption key to generate first encrypted data; and/or a second encryption module configured to decrypt the first encrypted data using the first encryption key, to output the decrypted first data to the second function module, and to encrypt second data output from the second function module using a second encryption key to generate second encrypted data. A semiconductor device may include: a bus; first and second modules configured to communicate via the bus; and/or an encryption module configured to use different encryption policies for first data, which is output from the first module and stored in a memory, and second data, which is output from the second module and stored in the memory.
-
公开(公告)号：US09633185B2
公开(公告)日：2017-04-25
申请号：US14556397
申请日：2014-12-01
发明人： Jonghoon Shin , KyoungMoon Ahn , Mijung Noh , Yong Ki Lee , Sun-Soo Shin
IPC分类号： G06F21/00 , G06F21/31 , G06F21/60 , G01R31/3185
CPC分类号： G06F21/31 , G01R31/318588 , G06F21/602
摘要： A method of debugging a device which includes a plurality of processors is provided. The method includes verifying a request to initiate authentication that is provided to the device to a user; performing a challenge-response authentication operation between the user and the device in response to the request to initiate authentication being a request from a non-malicious user; activating or deactivating an access to a Joint Test Action Group (JTAG) port of each of the processors, based on access control information from the user; and permitting a debugging operation via an access that is activated.
-
9.发明申请Arithmetic Devices, Montgomery Parameter Calculation Method and Modular Multiplication Method Thereof 审中-公开算术设备，蒙哥马利参数计算方法和模块化乘法方法公开(公告)号：US20160034255A1
公开(公告)日：2016-02-04
申请号：US14722761
申请日：2015-05-27
发明人： Sun-Soo Shin , Jonghoon Shin , KyoungMoon Ahn , Yong Ki Lee
IPC分类号： G06F7/523
CPC分类号： G06F7/728
摘要： Disclosed are arithmetic devices, a method of a Montgomery parameter calculation thereof and a Montgomery multiplication method thereof. The method of the Montgomery parameter calculation of the arithmetic devices includes detecting a position of a most significant bit (MSB) of a modulus, calculating an initial value using position information about the detected MSB, and calculating an intermediate value and a Montgomery parameter by repeatedly performing a Montgomery addition or a Montgomery multiplication with respect to the initial value.
摘要翻译： 公开了算术装置，其计算Montgomery参数的方法和Montgomery乘法方法。 算术装置的蒙哥马利参数计算方法包括检测模数的最高有效位（MSB）的位置，使用关于检测到的MSB的位置信息计算初始值，并通过重复地计算中间值和蒙哥马利参数 执行Montgomery加法或Montgomery乘法相对于初始值。
-
公开(公告)号：US20130311531A1
公开(公告)日：2013-11-21
申请号：US13734520
申请日：2013-01-04
发明人： KYOUNGMOON AHN , Jonghoon Shin , Yong Ki Lee , Ji-su Kang , Sun-soo Shin
IPC分类号： G06F7/72
摘要： A modular arithmetic unit includes a first input generator receiving first data to generate a first operand; a second input generator receiving second data to generate a second operand; an accumulator performing an accumulate/shift operation to add the first and second operands and outputting the carry and sum; a carry propagation adder adding the carry and the sum to output a result; and a data handler receiving either external data or the result and outputting the first data and the second data.
摘要翻译： 模块运算单元包括接收第一数据以产生第一操作数的第一输入发生器; 接收第二数据以产生第二操作数的第二输入发生器; 累加器执行累加/移位操作以添加第一和第二操作数并输出进位和和; 一个进位传播加法器，加上进位和和输出一个结果; 以及接收外部数据或结果并输出第一数据和第二数据的数据处理器。
-
-
-
-
-
-
-
-
-
搜索结果
17 条记录 (耗时 0.016 秒)
