公开(公告)号：USD1015344S1

公开(公告)日：2024-02-20

申请号：US29822524

申请日：2022-01-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Designer： Jieun Jeong ,  Changhwan Kim ,  Sungchan Bae ,  Seockhyun Yu ,  Yuri Choi

Abstract: FIG. 1 is a front view of a display screen or portion thereof with transitional graphical user interface showing a first image in a sequence, showing our new design;
FIG. 2 is a front view showing a second image thereof; and,
FIG. 3 is a front view showing a third image thereof.
The outermost perimeter illustrated by dashed broken lines represents display screens or portions thereof and forms no part of the claimed design. The remaining dashed broken lines illustrating portions of the graphical user interface form no part of the claimed design.
The appearance of the transitional graphical user interface sequentially transitions between the images shown in FIGS. 1-3. The process or period in which one image transitions to another image forms no part of the claimed design.
The contrast shown in grayscale in the figures represents a contrast of appearance.

公开(公告)号：US11609874B2

公开(公告)日：2023-03-21

申请号：US17347769

申请日：2021-06-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiwoong Kim ,  Dongjoo Kim ,  Jaekuk Park ,  Yujin Oh ,  Moonki Jang ,  Jieun Jeong

IPC: G06F11/07 ,  G06F11/14 ,  G06F13/40 ,  G06F13/38 ,  B60T7/12 ,  B60R16/023 ,  H04L12/40

Abstract: A system-on-chip (SoC) includes a processor, a system interconnect (a first bus) connected to the processor, a physical layer protocol (PHY) intellectual property (IP) block, a second bus connected to the processor, and a reset controller connected to the first bus and the second bus. The processor includes a plurality of central processing unit (CPU) cores. The PHY IP block, connected to the first bus, includes a plurality of PHY IPs including physical layers and is connected to external devices. The reset controller detects an abnormal state of the processor based on a signal from the processor, or an absence of a signal from the processor. The reset controller applies a reset signal to the PHY IP block in response to the detected abnormal state. The PHY IP block outputs a corresponding preset data to respective one of the external devices in response to the reset signal during a reset period.

公开(公告)号：US11074207B1

公开(公告)日：2021-07-27

申请号：US16929260

申请日：2020-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiwoong Kim ,  Dongjoo Kim ,  Jaekuk Park ,  Yujin Oh ,  Moonki Jang ,  Jieun Jeong

IPC: G06F11/07 ,  G06F11/14 ,  G06F13/40 ,  G06F13/38 ,  B60T7/12 ,  H04L12/40 ,  B60R16/023

Abstract: A system-on-chip (SoC) includes a processor, a system interconnect (a first bus) connected to the processor, a physical layer protocol (PHY) intellectual property (IP) block, a second bus connected to the processor, and a reset controller connected to the first bus and the second bus. The processor includes a plurality of central processing unit (CPU) cores. The PHY IP block, connected to the first bus, includes a plurality of PHY IPs including physical layers and is connected to external devices. The reset controller detects an abnormal state of the processor based on a signal from the processor, or an absence of a signal from the processor. The reset controller applies a reset signal to the PHY IP block in response to the detected abnormal state. The PHY IP block outputs a corresponding preset data to respective one of the external devices in response to the reset signal during a reset period.

公开(公告)号：USD1060378S1

公开(公告)日：2025-02-04

申请号：US29827975

申请日：2022-02-23

Applicant: Samsung Electronics Co., Ltd.

Designer： Jieun Jeong ,  Changhwan Kim ,  Sungchan Bae ,  Yuri Choi

公开(公告)号：US11934850B2

公开(公告)日：2024-03-19

申请号：US17881228

申请日：2022-08-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yuri Choi ,  Changhwan Kim ,  Sungchan Bae ,  Jieun Jeong

IPC: G06F3/04883 ,  G06F3/04845 ,  G06F3/0486 ,  G06F9/451 ,  G06F3/041

CPC classification number: G06F9/452 ,  G06F3/04845 ,  G06F3/0486 ,  G06F3/04883 ,  G06F3/0414

Abstract: An electronic device is disclosed and includes a display and at least one processor operatively connected with the display. The at least one processor is configured to, when an application is executed, display an execution window corresponding to the application on the display, display the execution window, as a first shape of execution window, on at least a portion of the display, in response to a background switch request for the application, identify a state of the application while displaying the first shape of execution window, and switch the first shape of execution window into a second shape of execution window according to the state of the application.

公开(公告)号：USD1013718S1

公开(公告)日：2024-02-06

申请号：US29827967

申请日：2022-02-23

Applicant: Samsung Electronics Co., Ltd.

Designer： Jieun Jeong ,  Yuri Choi ,  Changhwan Kim ,  Sungchan Bae ,  Seockhyun Yu

Abstract: FIG. 1 is the first image in a sequence for a display screen or portion thereof with animated graphical user interface showing our new design in accordance with a first embodiment;
FIG. 2 is the second image thereof;
FIG. 3 is the first image in a sequence for a display screen or portion thereof with animated graphical user interface showing our new design in accordance with a second embodiment;
FIG. 4 is the second image thereof;
FIG. 5 is the third image thereof; and,
FIG. 6 is the fourth image thereof.
The outer perimeter broken lines in the drawings represent a display screen or portion thereof and form no part of the claimed design. The remaining broken lines in the drawings illustrate portions of the animated graphical user interface that form no part of the claimed design.
The appearance of the animated images sequentially transition between the images shown in FIGS. 1-2, and 3-6, respectively. The process or period in which one image transitions to another image forms no part of the claimed design.

公开(公告)号：USD997189S1

公开(公告)日：2023-08-29

申请号：US29822719

申请日：2022-01-11

Applicant: Samsung Electronics Co., Ltd.

Designer： Jieun Jeong ,  Changhwan Kim ,  Sungchan Bae ,  Seockhyun Yu ,  Yuri Choi

Abstract: FIG. 1 is a front view of a first embodiment of an electronic device with transitional graphical user interface showing a first image in a sequence, showing our new design in a state that the electronic device is unfolded;
FIG. 2 is a front view showing a second image thereof, shown in a state that the electronic device is partially folded inward;
FIG. 3 is a perspective view of FIG. 1;
FIG. 4 is a perspective view of FIG. 2;
FIG. 5 is a right side view of FIG. 1;
FIG. 6 is a right side view of FIG. 2;
FIG. 7 is a front view of a second embodiment of an electronic device with transitional graphical user interface showing a first image in a sequence, showing our new design in a state that the electronic device is unfolded;
FIG. 8 is a front view showing a second image thereof, shown in a state that the electronic device is partially folded inward;
FIG. 9 is a perspective view of FIG. 7;
FIG. 10 is a perspective view of FIG. 8;
FIG. 11 is a right side view of FIG. 7; and,
FIG. 12 is a right side view of FIG. 8.
The outermost perimeter illustrated by dashed broken lines represents an electronic device and forms no part of the claimed design. The remaining dashed broken lines illustrating portions of the graphical user interface form no part of the claimed design.
The appearance of the transitional graphical user interface sequentially transitions between the images shown in FIGS. 1-2 or FIGS. 7-8. The process or period in which one image transitions to another image forms no part of the claimed design.
The contrast shown in grayscale in the figures represents a contrast of appearance.

公开(公告)号：US20210232521A1

公开(公告)日：2021-07-29

申请号：US16929260

申请日：2020-07-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jiwoong Kim ,  Dongjoo Kim ,  Jaekuk Park ,  Yujin Oh ,  Moonki Jang ,  Jieun Jeong

IPC: G06F13/38 ,  G06F11/07 ,  G06F11/14 ,  G06F13/40 ,  B60T7/12 ,  B60R16/023 ,  H04L12/40

Abstract: A system-on-chip (SoC) includes a processor, a system interconnect (a first bus) connected to the processor, a physical layer protocol (PHY) intellectual property (IP) block, a second bus connected to the processor, and a reset controller connected to the first bus and the second bus. The processor includes a plurality of central processing unit (CPU) cores. The PHY IP block, connected to the first bus, includes a plurality of PHY IPs including physical layers and is connected to external devices. The reset controller detects an abnormal state of the processor based on a signal from the processor, or an absence of a signal from the processor. The reset controller applies a reset signal to the PHY IP block in response to the detected abnormal state. The PHY IP block outputs a corresponding preset data to respective one of the external devices in response to the reset signal during a reset period.