公开(公告)号：US20250139194A1

公开(公告)日：2025-05-01

申请号：US18823847

申请日：2024-09-04

Applicant: Samsung Electronics Co., Ltd. ,  NAVER CORPORATION

Inventor： Younho JEON ,  Hong Rak SON ,  Wonsuk SONG ,  Younggeon YOO ,  JongYoon YOON ,  Jihoon LIM ,  Jae Hun JANG ,  Sejung KWON ,  Byeoungwook KIM ,  Baeseong PARK ,  Dongsoo LEE

IPC: G06F17/16 ,  G06F5/01 ,  H03M7/24

Abstract: A matrix multiplier includes an input vector scaler configured to generate a first scaled input vector based on a first input vector and a plurality of quantization scale coefficients, a first data type converter configured to generate a first fixed-point scaled input vector based on the first scaled input vector, a processing element array including a first processing element configured to generate a first fixed-point output element based on the first fixed-point scaled input vector and first plurality of quantization sign values and a second processing element configured to generate a second fixed-point output element based on the first fixed-point scaled input vector and second plurality of quantization sign values, and a second data type converter configured to generate first and second output elements by converting data type of the first and second fixed-point output elements, and to output a first output vector including the first and second output elements.

公开(公告)号：US20250117440A1

公开(公告)日：2025-04-10

申请号：US18817733

申请日：2024-08-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jae Hun JANG ,  Hong Rak SON ,  Dong-Min SHIN ,  JongYoon YOON ,  Jihoon LIM ,  Younho JEON ,  Dongsoo LEE ,  Sejung KWON ,  Byeoungwook KIM ,  Baeseong PARK

IPC: G06F17/16 ,  G06F5/01

Abstract: At least one embodiment provides a computing device including: a controller that receives first input data of a first data type and second input data of a second data type different from the first data type, and outputs a first signal representing the first data type, a second signal representing the second data type, and a clock signal based on the number of bits of the first input data and the second input data, and a computing circuit that performs a multiplication computation the first input data and the second input data based on the first signal, the second signal, and the clock signal and generates output data.

公开(公告)号：US20230163736A1

公开(公告)日：2023-05-25

申请号：US18058584

申请日：2022-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan MIN ,  Jahoon JIN ,  Soomin LEE ,  Sangho KIM ,  Jihoon LIM ,  Sodam JU ,  Hyunsu CHEA

IPC: H03F3/45

CPC classification number: H03F3/45179 ,  H03F2203/45116 ,  H03F2203/45222 ,  H03F2203/45601

Abstract: A self-bias signal generating circuit includes a differential amplifier circuit including a current source transistor. The differential amplifier circuit is configured to amplify at least a pair of differential input signals to generate at least a pair of differential output signals, and the differential amplifier circuit is configured to generate an output common-mode signal based on the at least a pair of differential output signals. The self-bias signal generating circuit includes a feedback loop circuit configured to adjust a voltage level of the output common-mode signal to generate a self-bias signal, and the feedback loop circuit is configured to provide the self-bias signal to the differential amplifier circuit. The self-bias signal is applied to a gate terminal of the current source transistor.

公开(公告)号：US20250139193A1

公开(公告)日：2025-05-01

申请号：US18820372

申请日：2024-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Younho JEON ,  Jae Hun JANG ,  Suchang KIM ,  Yeo-Reum PARK ,  Hong Rak SON ,  Jihoon LIM ,  Se Jung KWON ,  Byeoung Wook KIM ,  Baeseong PARK ,  Dongsoo LEE

IPC: G06F17/16

Abstract: A matrix multiplier includes an input vector scaler generating a first quantization scaled input vector based on a first input vector, a plurality of common scale coefficients, and first-to-Rth multiplication scale coefficients, a first data type converter generating a first fixed point quantization scaled input vector based on the first quantization scaled input vector, an element array comprising a first processing element generating a first fixed point output element based on the first fixed point quantization scaled input vector and first plurality of quantization sign bits, and a second processing element generating a second fixed point output element based on the first fixed point quantization scaled input vector and second plurality of quantization sign bits, and a second data type converter generating and outputting first and second output elements by converting data types of the first and second fixed point output elements.

公开(公告)号：US20230171134A1

公开(公告)日：2023-06-01

申请号：US17951482

申请日：2022-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jahoon JIN ,  Kyunghwan MIN ,  Soomin LEE ,  Sang-Ho KIM ,  Jihoon LIM ,  Sodam JU ,  Hyun Su CHEA

IPC: H04L25/03 ,  H04L7/00 ,  H04L1/20 ,  H04B1/16

CPC classification number: H04L25/03878 ,  H04L7/0079 ,  H04L1/205 ,  H04B1/16

Abstract: A semiconductor device including a comparison circuit configured to receive an input signal having n signal levels, where n is a natural number equal to or greater than three, and output n-1 first signals having two signal levels. The device includes a jitter compensation circuit configured to receive the n-1 first signals and compensate for at least one of a length of a period in which a signal level of at least one of the n-1 first signals transitions from a first signal level to a second signal level different from the first signal level, and a length of a period in which the signal level of the at least one of the n-1 first signals transitions from the second signal level to the first signal level, to output n-1 second signals.