公开(公告)号：US20230171134A1

公开(公告)日：2023-06-01

申请号：US17951482

申请日：2022-09-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jahoon JIN ,  Kyunghwan MIN ,  Soomin LEE ,  Sang-Ho KIM ,  Jihoon LIM ,  Sodam JU ,  Hyun Su CHEA

IPC: H04L25/03 ,  H04L7/00 ,  H04L1/20 ,  H04B1/16

CPC classification number: H04L25/03878 ,  H04L7/0079 ,  H04L1/205 ,  H04B1/16

Abstract: A semiconductor device including a comparison circuit configured to receive an input signal having n signal levels, where n is a natural number equal to or greater than three, and output n-1 first signals having two signal levels. The device includes a jitter compensation circuit configured to receive the n-1 first signals and compensate for at least one of a length of a period in which a signal level of at least one of the n-1 first signals transitions from a first signal level to a second signal level different from the first signal level, and a length of a period in which the signal level of the at least one of the n-1 first signals transitions from the second signal level to the first signal level, to output n-1 second signals.

公开(公告)号：US20240275390A1

公开(公告)日：2024-08-15

申请号：US18361059

申请日：2023-07-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jahoon JIN ,  Sangho KIM ,  Kyunghwan MIN ,  Soomin LEE ,  Sodam JU

IPC: H03L7/091 ,  H03L7/081

CPC classification number: H03L7/091 ,  H03L7/0816 ,  H03L2207/06

Abstract: Disclosed is a frequency detector. The frequency detector includes a first flip-flop sampling a clock signal based on a data signal to generate a first signal, a second flip-flop sampling a delayed-phase component of the clock signal based on the data signal or sampling the clock signal based on a delayed-phase component of the data signal to generate a second signal, a third flip-flop generating a third signal representing a polarity of a frequency difference between a data rate of the data signal and a frequency of the clock signal based on the first signal and the second signal, and a delay cell generating the delayed-phase component of the clock signal or the delayed-phase component of the data signal. The delayed-phase component has a delay amount set to a value smaller than about 0.25 UI.

公开(公告)号：US20230163736A1

公开(公告)日：2023-05-25

申请号：US18058584

申请日：2022-11-23

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan MIN ,  Jahoon JIN ,  Soomin LEE ,  Sangho KIM ,  Jihoon LIM ,  Sodam JU ,  Hyunsu CHEA

IPC: H03F3/45

CPC classification number: H03F3/45179 ,  H03F2203/45116 ,  H03F2203/45222 ,  H03F2203/45601

Abstract: A self-bias signal generating circuit includes a differential amplifier circuit including a current source transistor. The differential amplifier circuit is configured to amplify at least a pair of differential input signals to generate at least a pair of differential output signals, and the differential amplifier circuit is configured to generate an output common-mode signal based on the at least a pair of differential output signals. The self-bias signal generating circuit includes a feedback loop circuit configured to adjust a voltage level of the output common-mode signal to generate a self-bias signal, and the feedback loop circuit is configured to provide the self-bias signal to the differential amplifier circuit. The self-bias signal is applied to a gate terminal of the current source transistor.

公开(公告)号：US20240303214A1

公开(公告)日：2024-09-12

申请号：US18458332

申请日：2023-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jahoon JIN ,  Kyunghwan MIN ,  Sangho KIM ,  Hyoungjoong KIM ,  Soomin LEE ,  Sodam JU

IPC: G06F13/42 ,  H03K5/24

CPC classification number: G06F13/4282 ,  H03K5/24 ,  G06F2213/0002

Abstract: Disclosed is a receiver of a serial interface, comprising, a first multiplexer configured to select one of a data signal and a first reference voltage in response to an enable signal, a second multiplexer configured to select one of the first reference voltage and a second reference voltage in response to the enable signal, a comparator receiving an output of the first multiplexer to a positive input terminal and an output of the second multiplexer to a negative input terminal, and a reference generator configured to generate the second reference voltage and to generate the first reference voltage from the second reference voltage using an unity gain buffer.

公开(公告)号：US20240267197A1

公开(公告)日：2024-08-08

申请号：US18472796

申请日：2023-09-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyunghwan MIN ,  Sangho KIM ,  Soomin LEE ,  Sodam JU ,  Jahoon JIN

IPC: H04L7/033 ,  H04L7/00

CPC classification number: H04L7/0337 ,  H04L7/0091

Abstract: Provided is a method of correcting a clock, the method including receiving a first clock, a second clock, a third clock, and a fourth clock, correcting each of a second rising edge of the second clock, a third rising edge of the third clock, and a fourth rising edge of the fourth clock based on a first rising edge of the first clock, and correcting each of a first falling edge of the first clock, a second falling edge of the second clock, a third falling edge of the third clock, and a fourth falling edge of the fourth clock based on a first rising edge of the first clock.

公开(公告)号：US20220014195A1

公开(公告)日：2022-01-13

申请号：US17160888

申请日：2021-01-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hwang Ho CHOI ,  Yungeun NAM ,  Sodam JU

IPC: H03K19/0185 ,  H04L25/02 ,  G11C11/4093 ,  G11C7/10

Abstract: An interface circuit includes a first switch element connected to a first power supply node, supplying a first power supply voltage, and an output node, transmitting an output signal, and controlled by a first input signal, a second switch element connected to a second power supply node, supplying a second power supply voltage, lower than the first power supply voltage, and the output node and controlled by a second input signal, different from the first input signal, a first resistor connected between the first power supply node and the first switch element, a second resistor connected between the second power supply node and the second switch element, a first capacitor connected between the first resistor and the first switch element and charged and discharged by a first control signal, a second capacitor connected between the second resistor and the second switch element and charged and discharged by a second control signal, and a buffer circuit configured to output the first control signal and the second control signal and connected to a third power supply node, supplying a third power supply voltage, through a first variable resistor and connected to a fourth power supply node, supplying a fourth power supply voltage, lower than the third power supply node, through a second variable resistor.