公开(公告)号：US20200250106A1

公开(公告)日：2020-08-06

申请号：US16637487

申请日：2018-09-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dong-uk KIM ,  Jin-bum PARK

IPC: G06F12/14 ,  G06F12/0871 ,  G06F12/04 ,  G06F21/57 ,  G06F9/455

Abstract: Disclosed are an electronic device and a control method thereof. The electronic device according to the present disclosure includes a memory, a cache memory, a CPU, and includes a processor which controls the electronic device by using a program stored in the memory, wherein the CPU monitors an input address through which an input value is accessed in the cache memory, and changes the input address when the input address through which the input value is accessed in the cache memory is changed to a preset pattern.

公开(公告)号：US20190121966A1

公开(公告)日：2019-04-25

申请号：US16035196

申请日：2018-07-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-bum PARK ,  Dong-uk KIM

IPC: G06F21/54 ,  G06F21/56

Abstract: Provided is a method, performed by a device, of protecting information from a side channel attack, the method including: loading a library shared by at least one application installed in the device to a memory of a first layer; inputting a value to a function of the library; based on the value being input, detecting a region of the memory accessed by the device from among regions of the memory of the first layer, to which the library is loaded; generating a protection code which accesses regions of the memory other than the detected region from among the regions of the memory of the first layer, to which the library is loaded; and adding the protection code to the function of the library.

公开(公告)号：US20170262383A1

公开(公告)日：2017-09-14

申请号：US15440283

申请日：2017-02-23

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Ki-hun LEE ,  Jong-oh HUR ,  Ji-hoon KIM ,  Jin-bum PARK ,  Dong-uk KIM

IPC: G06F12/14

Abstract: An electronic apparatus and a control method thereof are provided. The electronic apparatus includes a memory having a protection area and storing data of a first operating system (OS) and at least one first program involved with first OS in the protection area; at least one processor configured to execute the at least one first program and at least one second program involved with a second OS having an authority higher than the first OS; and a memory monitor comprising circuitry configured to detect whether an access to the protection area of the memory occurs, to interrupt the access if the access occurs, and to perform a security verification of the data stored in the protection area. The electronic apparatus may guarantee and/or improve integrity thereof using a hardware device, which can directly monitor the memory at a CPU environment in which a security area and a general area are separated.