公开(公告)号：US20190019758A1

公开(公告)日：2019-01-17

申请号：US15956414

申请日：2018-04-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sang-Uk KIM ,  Sunchul KIM ,  Jinkyeong SEOL ,  BYOUNG WOOK JANG

IPC: H01L23/538 ,  H01L23/31 ,  H01L23/00 ,  H01L25/10 ,  H01L25/00 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package and a method manufacturing the same are disclosed. At least one semiconductor chip is mounted on a package substrate. An insulative mold layer is formed at sides of the semiconductor chip having at least one recess in a region in which conductive connection members are formed, the recess defining one or more protrusions within the mold layer. An interposer is positioned on the protrusions with the conductive connection members connecting and providing electrical connections between conductive pads on the upper surface of the package and conductive pads on the lower surface of the package substrate. The protrusions may position the interposer in the vertical direction by defining the vertical spacing between the lower surface of the interposer and the upper surface of the package substrate. The protrusions may also position the interposer in one or more horizontal directions and/or prevent substantial movement during connecting of the interposer to the package substrate. An under-fill resin layer may be injected into remaining space between the interposer and the package substrate.

公开(公告)号：US20250157980A1

公开(公告)日：2025-05-15

申请号：US18741540

申请日：2024-06-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinkyeong SEOL

IPC: H01L23/00 ,  H01L23/48 ,  H01L23/498 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor package includes semiconductor chips each including at least one of a front insulating layer or a rear insulating layer, the semiconductor chips bonded to each other through direct bonding between the front insulating layer and the rear insulating layer. At least one of the semiconductor chips includes a device layer including an interconnection structure, and a conductive pattern on a front surface of the device layer. The conductive pattern includes pad patterns electrically connected to the interconnection structure, and a dummy pattern spaced apart from the pad patterns. The dummy pattern includes first dummy patterns between the pad patterns to overlap the pad patterns in a first direction, and a second dummy patterns between the first dummy patterns to overlap the pad patterns in the second direction. The second dummy patterns are spaced apart from the first dummy patterns.

公开(公告)号：US20250006676A1

公开(公告)日：2025-01-02

申请号：US18641504

申请日：2024-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinkyeong SEOL

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip including first bonding pads disposed in a first main region on a first surface of a first substrate, first dummy bonding pads disposed in a first peripheral region on the first surface of the first substrate, and a first passivation layer disposed on the first surface, and a second semiconductor chip on the first semiconductor chip and including a wiring layer on a third surface of a second substrate and including redistribution pads in a second main region, second bonding pads disposed on the redistribution pads, second dummy bonding pads disposed in a second peripheral region on the wiring layer, and a second passivation layer disposed on the wiring layer. The first bonding pads and the second bonding pads are directly bonded to each other. The first dummy bonding pads and the second dummy bonding pads are directly bonded to each other.

公开(公告)号：US20250140723A1

公开(公告)日：2025-05-01

申请号：US18671443

申请日：2024-05-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jihoon KIM ,  Jinkyeong SEOL ,  Raeyoung KANG ,  Minki KIM ,  Hyeonkyu HA

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065 ,  H10B80/00

Abstract: A semiconductor package includes a plurality of semiconductor chips bonded to each other through direct bonding, the plurality of semiconductor chips including a first semiconductor chip and a second semiconductor chip. The first semiconductor chip including: a front insulating layer bonded to a back insulating layer of the second semiconductor chip; a front pad surrounded by the front insulating layer; a device layer on a back surface of the front insulating layer and including an interconnection structure electrically connected to the front pad; a conductive pattern between the interconnection structure and the front pad; and a support insulating layer between the device layer and the front insulating layer and surrounding the conductive pattern, wherein a gap is between a first side surface of the support insulating layer and a second side surface of the conductive pattern that faces the first side surface.

公开(公告)号：US20210082881A1

公开(公告)日：2021-03-18

申请号：US16809837

申请日：2020-03-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinkyeong SEOL ,  Sunchul KIM ,  Pyoungwan KIM

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/16 ,  H01L23/532

Abstract: A semiconductor package including a substrate; a semiconductor stack on the substrate; an underfill between the substrate and the semiconductor stack; an insulating layer conformally covering surfaces of the semiconductor stack and the underfill; a chimney on the semiconductor stack; and a molding member surrounding side surfaces of the chimney, wherein the semiconductor stack has a first upper surface that is a first distance from the substrate and a second upper surface that is a second distance from the substrate, the first distance being greater than the second distance, wherein the chimney includes a thermally conductive filler on the first and second upper surfaces of the semiconductor stack, the thermally conductive filler having a flat upper surface; a thermally conductive spacer on the thermally conductive filler; and a protective layer on the thermally conductive spacer, and wherein an upper surface of the thermally conductive spacer is exposed.