公开(公告)号：US11189533B2

公开(公告)日：2021-11-30

申请号：US16390345

申请日：2019-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Hyun Choi ,  Seok-Bae Moon ,  Jae-Hyuk Choi ,  Won-Ki Park ,  Jong-Hwi Seo

IPC: H01L21/265 ,  H01L21/66 ,  H01J37/317

Abstract: A method of inspecting a wafer quality includes injecting ions into a wafer using an ion beam in an ion implantation process, collecting data about the ion beam by using a Faraday cup, extracting first data from the data about the ion beam, extracting a wafer section from the first data, calculating a feature value of a wafer from the wafer section, and evaluating a quality of the wafer by comparing the feature value with a predetermined threshold or range.

公开(公告)号：US20200091012A1

公开(公告)日：2020-03-19

申请号：US16390345

申请日：2019-04-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Hyun Choi ,  Seok-Bae Moon ,  Jae-Hyuk Choi ,  Won-Ki Park ,  Jong-Hwi Seo

IPC: H01L21/66 ,  H01J37/317

Abstract: A method of inspecting a wafer quality includes injecting ions into a wafer using an ion beam in an ion implantation process, collecting data about the ion beam by using a Faraday cup, extracting first data from the data about the ion beam, extracting a wafer section from the first data, calculating a feature value of a wafer from the wafer section, and evaluating a quality of the wafer by comparing the feature value with a predetermined threshold or range.

公开(公告)号：US09620193B2

公开(公告)日：2017-04-11

申请号：US14793749

申请日：2015-07-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Doo-Hee Hwang ,  Sang-Kyu Kang ,  Dong-Yang Lee ,  Jae-Yeon Choi ,  Jong-Hyun Choi

IPC: G11C7/00 ,  G11C11/406 ,  G11C7/10

CPC classification number: G11C11/40611 ,  G11C7/1063 ,  G11C11/406

Abstract: A semiconductor memory device includes a memory cell array and a refresh control circuit. The memory cell array includes a plurality of memory cell rows. The refresh control circuit performs a normal refresh operation on the plurality of memory cell rows and performs a weak refresh operation on a plurality of weak pages of the plurality of memory cell rows. Each of the weak pages includes at least one weak cell whose data retention time is smaller than normal cells. The refresh control circuit transmits a refresh flag signal to a memory controller external to the semiconductor memory device when the refresh control circuit performs the weak refresh operation on the weak pages in a normal access mode.